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    Deep trench capacitor with buried plate electrode and isolation collar
    1.
    发明授权
    Deep trench capacitor with buried plate electrode and isolation collar 有权
    深沟槽电容器，埋置电极和隔离环

    公开(公告)号：US07122437B2

    公开(公告)日：2006-10-17

    申请号：US10741203

    申请日：2003-12-19

    申请人： Thomas W. Dyer ,  Chun-yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Carl Radens

    发明人： Thomas W. Dyer ,  Chun-yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Carl Radens

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1087 ,  H01L29/945

    摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.

    摘要翻译： 在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。 深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。 掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。 当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。 掩埋板区域与隔离套环自对准。 通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。

    Method for fabricating a trench having a buried dielectric collar
    2.
    发明授权
    Method for fabricating a trench having a buried dielectric collar 失效
    一种用于制造具有埋入式电介质套环的沟槽的方法

    公开(公告)号：US06933192B1

    公开(公告)日：2005-08-23

    申请号：US10709472

    申请日：2004-05-07

    申请人： Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Chun-Yung Sung

    发明人： Ramachandra Divakaruni ,  Ravikumar Ramachandran ,  Chun-Yung Sung

    IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L29/94

    CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945

    摘要： A method of forming a buried dielectric collar around a trench and of forming a trench capacitor, the buried dielectric collar formed by: (a) forming the trench in a substrate; (b) forming a multilayer coating on sidewalls and a bottom of the trench; (c) removing a continuous band of the multilayer coating from the sidewalls a fixed distance from a top of the trench to expose a continuous band substrate in the sidewalls of the trench; (d) etching, in said exposed band of substrate, a lateral trench extending into said substrate in said sidewalls of said trench; and (e) filling the lateral trench with a dielectric material to form the buried dielectric collar. The trench capacitor is formed by filling the trench or its variants with polysilicon.

    摘要翻译： 一种在沟槽周围形成埋置的介电环圈并形成沟槽电容器的方法，所述埋入介质套管由以下部分形成：（a）在衬底中形成沟槽; （b）在沟槽的侧壁和底部上形成多层涂层; （c）从沟槽的顶部固定的距离从侧壁去除多层涂层的连续带，以暴露在沟槽的侧壁中的连续带状衬底; （d）在所述衬底的所述暴露带中蚀刻在所述沟槽的所述侧壁中延伸到所述衬底中的横向沟槽; 和（e）用电介质材料填充横向沟槽以形成埋入的电介质套环。 通过用多晶硅填充沟槽或其变体形成沟槽电容器。

    Deep trench capacitor with buried plate electrode and isolation collar
    3.
    发明申请
    Deep trench capacitor with buried plate electrode and isolation collar 有权
    深沟槽电容器，埋置电极和隔离环

    公开(公告)号：US20050133846A1

    公开(公告)日：2005-06-23

    申请号：US10741203

    申请日：2003-12-19

    申请人： Thomas Dyer ,  Chun-Yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni

    发明人： Thomas Dyer ,  Chun-Yung Sung ,  Ravikumar Ramachandran ,  Ramachandra Divakaruni

    IPC分类号： H01L21/8242 ,  H01L29/94 ,  H01L27/108 ,  H01L31/119

    CPC分类号： H01L27/1087 ,  H01L29/945

    摘要： A deep trench capacitor used in a trench DRAM includes a buried plate and an isolation collar. The deep trench is bottle-shaped, and the isolation collar is formed in upper portion of the wider region of the bottle-shaped trench. The buried plate surrounds the lower portion of the wider part of the bottle-shaped trench, and hemispherical grain polysilicon lines the walls of at least the lower portion of the wider part of the trench. A nitride liner layer lines the inner walls of the oxide collar and prevents diffusion of dopant through the oxide collar into the substrate when the HSG polysilicon and the doped buried plate are formed. The buried plate region is self-aligned to the isolation collar. The depth of the top of the wider part of the bottle shape and the bottom depth of the isolation collar are determined by successive resist deposition and recessing steps.

    摘要翻译： 在沟槽DRAM中使用的深沟槽电容器包括掩埋板和隔离环。 深沟是瓶形的，并且隔离套环形成在瓶形沟槽的较宽区域的上部。 掩埋板围绕瓶形沟槽的较宽部分的下部，半球状晶粒多晶硅线路至少沟槽较宽部分的下部的壁。 当形成HSG多晶硅和掺杂掩埋板时，氮化物衬垫层线化氧化物环的内壁并防止掺杂剂通过氧化物环到衬底中的扩散。 掩埋板区域与隔离套环自对准。 通过连续的抗蚀剂沉积和凹陷步骤确定瓶子形状的较宽部分的顶部的深度和隔离环的底部深度。

    Replacement Gate With Reduced Gate Leakage Current
    4.
    发明申请
    Replacement Gate With Reduced Gate Leakage Current 审中-公开
    降低闸门泄漏电流的更换门

    公开(公告)号：US20130256802A1

    公开(公告)日：2013-10-03

    申请号：US13430755

    申请日：2012-03-27

    申请人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

    发明人： Hemanth Jagannathan ,  Ramachandra Divakaruni ,  Unoh Kwon ,  Vijay Narayanan ,  Ravikumar Ramachandran

    IPC分类号： H01L27/088 ,  H01L21/283

    CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/105 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material, which provides, in combination with other layer, a work function about 4.4 eV or less, and can include a material selected from tantalum carbide, metallic nitrides, and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel. Optionally, carbon doping can be introduced in the channel.

    摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括与其它层组合提供约4.4eV或更低的功函数的材料，并且可以包括选自碳化钽，金属氮化物和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。 任选地，可以在通道中引入碳掺杂。

    Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current
    5.
    发明申请
    Replacement Metal Gate Structures Providing Independent Control On Work Function and Gate Leakage Current 失效
    替代金属栅极结构提供工作功能和栅极泄漏电流的独立控制

    公开(公告)号：US20120132998A1

    公开(公告)日：2012-05-31

    申请号：US12954946

    申请日：2010-11-29

    申请人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    发明人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    IPC分类号： H01L27/092 ,  H01L21/336

    CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

    摘要翻译： 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类型场效应晶体管的区域中的势垒金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。

    Self-Aligned Contacts for High k/Metal Gate Process Flow
    7.
    发明申请
    Self-Aligned Contacts for High k/Metal Gate Process Flow 有权
    用于高k /金属栅极工艺流程的自对准触点

    公开(公告)号：US20120175711A1

    公开(公告)日：2012-07-12

    申请号：US12987221

    申请日：2011-01-10

    申请人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    发明人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    IPC分类号： H01L29/772 ,  H01L21/283

    CPC分类号： H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

    摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

    摘要翻译： 提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。 每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。 间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。 每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。 接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。 该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。 还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

    Self-aligned contacts for high k/metal gate process flow
    8.
    发明授权
    Self-aligned contacts for high k/metal gate process flow 有权
    用于高k /金属栅极工艺流程的自对准触点

    公开(公告)号：US08536656B2

    公开(公告)日：2013-09-17

    申请号：US12987221

    申请日：2011-01-10

    申请人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    发明人： Ravikumar Ramachandran ,  Ramachandra Divakaruni ,  Ying Li

    IPC分类号： H01L21/70

    CPC分类号： H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

    摘要： A semiconductor structure is provided that includes a semiconductor substrate having a plurality of gate stacks located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer, a work function metal layer and a conductive metal. A spacer is located on sidewalls of each gate stack and a self-aligned dielectric liner is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner is present on an upper surface of a semiconductor metal alloy. A contact metal is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner. The structure also includes another contact metal having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

    摘要翻译： 提供一种半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层的半导体衬底。 每个栅极堆叠包括从底部到顶部的高k栅极电介质层，功函数金属层和导电金属。 间隔件位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫存在于每个间隔件的上表面上。 每个自对准电介质衬垫的底表面存在于半导体金属合金的上表面上。 接触金属位于相邻的栅极堆叠之间，并通过自对准电介质衬垫与每个栅极堆叠分离。 该结构还包括另一个接触金属，其具有位于接触金属的上表面上且与触头金属的上表面直接接触的部分，以及位于与其中一个栅极叠层的导电金属直接接触的另一部分。 还公开了使用替换栅极和非替代栅极方案形成半导体结构的方法。

    Replacement metal gate structures providing independent control on work function and gate leakage current
    9.
    发明授权
    Replacement metal gate structures providing independent control on work function and gate leakage current 失效
    替代金属栅极结构提供对功函数和栅极漏电流的独立控制

    公开(公告)号：US08450169B2

    公开(公告)日：2013-05-28

    申请号：US12954946

    申请日：2010-11-29

    申请人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    发明人： Unoh Kwon ,  Ramachandra Divakaruni ,  Siddarth A. Krishnan ,  Ravikumar Ramachandran

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/092 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

    摘要： The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures.

    摘要翻译： 可以通过平面高介电常数材料部分为不同类型的场效应晶体管选择栅极电介质的厚度和组成，其可以仅针对选定类型的场效应晶体管提供。 此外，场效应晶体管的工作功能可以独立于栅极电介质的材料堆叠的选择而被调整。 在去除一次性栅极材料部分之后，在凹入的栅极腔内的栅极电介质层上沉积阻挡金属层和第一类型功函数金属层的堆叠。 图案化第一型功函数金属层之后，第二类功函数金属层直接沉积在第二类场效应晶体管的区域中的阻挡金属层上。 导电材料填充栅极腔，随后的平坦化工艺形成双功能金属栅极结构。