公开(公告)号：US20100255426A1

公开(公告)日：2010-10-07

申请号：US12419210

申请日：2009-04-06

申请人： Kanti JAIN ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

发明人： Kanti JAIN ,  Junghun Chae ,  Kevin Lin ,  Hyunjong Jin

IPC分类号： G03F7/20 ,  B32B37/02 ,  G02B5/08 ,  G02B1/10 ,  G02B26/00 ,  G02B26/02

CPC分类号： G02B26/0833 ,  G02B5/0833 ,  G02B5/0858 ,  G03F7/70291

摘要： Micromirrors and micromirror arrays described herein are useful, for example in maskless photolithography systems and methods and projection display devices and methods. According to one aspect, the micromirrors comprise a polymer structural layer and a reflective dielectric multilayer for selective reflection and/or redirection of incoming electromagnetic radiation. According to another aspect, incorporation of a reflective dielectric multilayer allows for use of polymer structural materials in micromirrors and prevents damage to such polymer materials due to excessive heating from absorption of electromagnetic radiation, as the reflective dielectric multilayers are highly reflective and minimize heating of the micromirror components. According to yet a further aspect, top down fabrication methods are described herein for making a micromirror comprising a polymer structural layer and a reflective dielectric multilayer.

摘要翻译： 本文所述的微镜和微镜阵列是有用的，例如在无掩模光刻系统和方法以及投影显示装置和方法中。 根据一个方面，微镜包括用于选择性反射和/或重定向输入电磁辐射的聚合物结构层和反射电介质多层。 根据另一方面，引入反射电介质多层允许在微反射镜中使用聚合物结构材料，并且防止由于电磁辐射的吸收导致的过度加热而损坏这种聚合物材料，因为反射电介质多层是高度反射性的并且使得 微镜组件。 根据又一方面，本文描述了自顶向下的制造方法，用于制造包括聚合物结构层和反射电介质多层的微镜。

公开(公告)号：US20090239042A1

公开(公告)日：2009-09-24

申请号：US12052980

申请日：2008-03-21

申请人： Kanti JAIN ,  Junghun CHAE

发明人： Kanti JAIN ,  Junghun CHAE

IPC分类号： B32B3/10 ,  B29C35/08 ,  B05D5/12 ,  C23C16/453 ,  C23C16/50 ,  G03F7/20

CPC分类号： H01L21/3213 ,  B23K26/0006 ,  B23K26/18 ,  B23K26/352 ,  B23K26/40 ,  B23K2103/08 ,  B23K2103/42 ,  B23K2103/50 ,  B23K2103/52 ,  B23K2103/56 ,  B81C1/00634 ,  B82Y20/00 ,  B82Y30/00 ,  G03F7/202 ,  Y10T428/24802

摘要： This invention provides photoablation—based processing techniques and materials strategies for making, assembling and integrating patterns of materials for the fabrication of electronic, optical and opto-electronic devices. Processing techniques of the present invention enable high resolution and/or large area patterning and integration of porous and/or nano- or micro-structured materials comprising active or passive components of a range of electronic devices, including integrated circuits (IC), microelectronic and macroelectronic systems, microfluidic devices, biomedical devices, sensing devices and device arrays, and nano- and microelectromechanical systems.

摘要翻译： 本发明提供了用于制造，组装和集成用于制造电子，光学和光电子器件的材料的图案的基于光消息的处理技术和材料策略。 本发明的加工技术能够实现高分辨率和/或大面积图案化和多孔和/或纳米或微结构材料的整合，包括一系列电子器件的有源或无源元件，包括集成电路（IC），微电子和 宏观电子系统，微流体装置，生物医学装置，感测装置和装置阵列以及纳米和微机电系统。

公开(公告)号：US20140134404A1

公开(公告)日：2014-05-15

申请号：US14157407

申请日：2014-01-16

申请人： Kanti JAIN ,  Uttam REDDY

发明人： Kanti JAIN ,  Uttam REDDY

IPC分类号： H05K3/10

CPC分类号： H05K3/107 ,  H01L21/0277 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76813 ,  H01L2221/1021

摘要： This invention provides processing steps, methods and materials strategies for making patterns of structures for integrated electronic devices and systems. Processing methods of the present invention are capable of making micro- and nano-scale structures, such as Dual Damascene profiles, recessed features and interconnect structures, having non-uniform cross-sectional geometries useful for establishing electrical contact between device components of an electronic device. The present invention provides device fabrication methods and processing strategies using sub pixel-voting lithographic patterning of a single layer of photoresist useful for fabricating and integrating multilevel interconnect structures for high performance electronic or opto-electronic devices, particularly useful for Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices. Processing methods of the present invention are complementary to conventional microfabrication and nanofabrication methods for making integrated electronics, and can be effectively integrated into existing photolithographic, etching, and thin film deposition patterning systems, processes and infrastructure.

摘要翻译： 本发明提供了用于制造集成电子设备和系统的结构图案的处理步骤，方法和材料策略。 本发明的加工方法能够制造具有非均匀横截面几何形状的微米和纳米级结构，例如双镶嵌型材，凹形特征和互连结构，其用于建立电子装置的装置部件之间的电接触 。 本发明提供了使用用于制造和集成用于高性能电子或光电子器件的多层互连结构的单层光致抗蚀剂的子像素投影光刻图案的器件制造方法和处理策略，特别适用于超大规模集成（VLSI ）和超大规模集成（ULSI）设备。 本发明的加工方法与用于制造集成电子学的常规微细加工和纳米制造方法互补，并且可以有效地集成到现有的光刻，蚀刻和薄膜沉积图案化系统，工艺和基础设施中。