公开(公告)号：US5371517A

公开(公告)日：1994-12-06

申请号：US791757

申请日：1991-11-08

申请人： Louis Izzi ,  William R. Krenik ,  Henry T. Yung ,  Chenwei J. Yin ,  Carrell R. Killebrew, Jr. ,  Karl Guttag ,  Jerry R. Van Aken ,  Jeffrey Nye ,  Richard Simpson ,  Mike Asal

发明人： Louis Izzi ,  William R. Krenik ,  Henry T. Yung ,  Chenwei J. Yin ,  Carrell R. Killebrew, Jr. ,  Karl Guttag ,  Jerry R. Van Aken ,  Jeffrey Nye ,  Richard Simpson ,  Mike Asal

IPC分类号： G06F11/00 ,  G09G5/06 ,  G09G5/18 ,  G09G1/28

CPC分类号： G06F11/006 ,  G09G5/06 ,  G09G5/18

摘要： A color palette selects a master clock from plural clock signals received at clock input terminals in response to a master clock selection control word received at control data terminals. A circuit forms a plurality of divided down clock signals from selected divide ratios of the master clock. A circuit selects a shift clock from among the divided down clock signals in response to at least some bits of an output clock selection control word received at the control data terminals. A circuit selectively enables and disables the shift clock in response to blanking data. A circuit selects a video clock from among the divided down clock signals in response to at least some bits of the output clock selection control word. A circuit synchronizes multiple bit words of color code received at color code input terminals with the master clock. A circuit outputs at least one memory recall address in response to receiving each multiple bit word of color code. A circuit stores color data words in a plurality of data storage locations, having associated memory recall addresses, and outputs a color data word upon receipt of an associated memory recall address. A circuit selectively writes color data words into these plural locations. A circuit synchronizes video control signals received at video control terminals with the master clock and provides the blanking data. A circuit selects for output between said color data words and true color data words received at said color code input terminals.

摘要翻译： 响应于在控制数据终端接收的主时钟选择控制字，调色板从在时钟输入端接收的多个时钟信号中选择主时钟。 A电路根据主时钟的选择的分频比形成多个分频的下降时钟信号。 电路响应于在控制数据端子处接收的输出时钟选择控制字的至少一些位，从分频的下降时钟信号中选择移位时钟。 电路响应于消隐数据选择性地启用和禁用移位时钟。 响应于输出时钟选择控制字的至少一些位，电路从分频的下降时钟信号中选择视频时钟。 电路将彩色码输入端子接收的彩色码的多位字与主时钟同步。 响应于接收到颜色代码的每个多个位字，A电路输出至少一个存储器调用地址。 电路将颜色数据字存储在具有相关联的存储器调用地址的多个数据存储位置中，并且在接收到相关联的存储器调用地址时输出彩色数据字。 电路将彩色数据字选择性地写入这些多个位置。 电路将视频控制终端接收的视频控制信号与主时钟同步，并提供消隐数据。 电路选择所述颜色数据字和在所述颜色代码输入端接收的真彩色数据字之间的输出。

公开(公告)号：US5596583A

公开(公告)日：1997-01-21

申请号：US734344

申请日：1991-07-19

申请人： William R. Krenik ,  Louis J. Izzi ,  Chenwei J. Yin

发明人： William R. Krenik ,  Louis J. Izzi ,  Chenwei J. Yin

IPC分类号： G11C29/14 ,  G11C29/48 ,  G01R31/28

CPC分类号： G11C29/48 ,  G11C29/14

摘要： Test circuitry (90) is provided which includes a multiplexer (118) for selectively receiving multiple bit control words defining test functions to be executed by said test circuitry and for outputting data from said test circuitry. A plurality of digital data inputs (96) are provided for receiving multiple bit words of digital data and a plurality of analog data inputs (98) are provided for receiving analog data. A register (120) is coupled to multiplexer (118) for storing a one of the multiple bit words received by multiplexer (118). Control circuitry (122) is coupled to register (120) for controlling execution of the test function defined by the control word being held in register (120). First test circuitry (112) is coupled to digital data inputs (96) and control circuitry (122) for passing digital data words received at digital data inputs (96) to multiplexer (118) for output in response to a first control word of said control words being held in register (120).

摘要翻译： 提供了测试电路（90），其包括多路复用器（118），用于选择性地接收定义由所述测试电路执行的测试功能的多个位控制字，并用于从所述测试电路输出数据。 提供多个数字数据输入（96）用于接收数字数据的多位字，并且提供多个模拟数据输入（98）用于接收模拟数据。 寄存器（120）耦合到多路复用器（118），用于存储由多路复用器（118）接收的多个位字之一。 控制电路（122）耦合到寄存器（120），用于控制由保持在寄存器（120）中的控制字定义的测试功能的执行。 第一测试电路（112）耦合到数字数据输入（96）和控制电路（122），用于将数字数据输入（96）接收的数字数据字传送到多路复用器（118），以响应于所述第一控制字 控制字被保存在寄存器（120）中。

公开(公告)号：US5469195A

公开(公告)日：1995-11-21

申请号：US288137

申请日：1994-08-09

申请人： Henry T. Yung ,  Louis J. Izzi ,  William R. Krenik

发明人： Henry T. Yung ,  Louis J. Izzi ,  William R. Krenik

IPC分类号： H01L27/08 ,  G09G1/28

CPC分类号： H01L27/0805

摘要： An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.

摘要翻译： 集成电路电容器具有半导体管芯和在管芯上制造并具有栅极，源极和漏极的多个场效应晶体管。 栅极作为电容器的一侧彼此连接。 源极和漏极连接在一起作为电容器的另一侧。 调色板具有包括具有连接到电源轨的晶体管的点时钟缓冲器的电路的芯片，并且集成电路电容器具有连接在电源轨上的多个并联连接的场效应晶体管。 点时钟缓冲器具有直接分配到电路的其余部分的输出。 还公开了其它电容器，缓冲器，系统和方法。

公开(公告)号：US09033508B2

公开(公告)日：2015-05-19

申请号：US13319317

申请日：2010-05-07

申请人： Michael Bartlett ,  William R. Krenik ,  Yi-Zhong Wang

发明人： Michael Bartlett ,  William R. Krenik ,  Yi-Zhong Wang

IPC分类号： A61B3/02 ,  A61B3/032 ,  A61B3/00

CPC分类号： A61B3/032 ,  A61B3/0033 ,  A61B3/005 ,  A61B3/0066 ,  A61B3/0075 ,  A61B5/14532 ,  G09G2380/08 ,  H04N5/351

摘要： In one aspect, there is provided a handheld vision tester comprising a display, cursor control, interface port, and camera. The display delivers a series of images making up vision tests to a user who interacts with the vision tests by using the display and cursor control of the handheld vision tester. The camera verifies the user is taking the vision tests. The results of the vision tests are stored in the handheld communication device. The interface port allows for communication of the stored results of the vision tests with external devices. In another aspect, there is provided a calibration system for the handheld vision tester. The calibration system includes a stand to hold the handheld vision tester and a reflective surface substantially parallel to a display of the handheld vision tester.

摘要翻译： 一方面，提供了一种包括显示器，光标控制，接口端口和照相机的手持式视觉测试仪。 该显示器通过使用手持式视觉测试仪的显示和光标控制，向与视觉测试交互的用户提供构成视觉测试的一系列图像。 相机验证用户正在进行视力测试。 视觉测试的结果存储在手持通信设备中。 接口端口允许将存储的视觉测试结果与外部设备进行通信。 另一方面，提供了一种用于手持视觉测试仪的校准系统。 校准系统包括支架，用于支撑手持式视觉测试仪和基本平行于手持视觉测试仪的显示器的反射表面。

公开(公告)号：US08668334B2

公开(公告)日：2014-03-11

申请号：US11679564

申请日：2007-02-27

申请人： William R. Krenik

发明人： William R. Krenik

IPC分类号： A61B3/10

CPC分类号： A61H5/005 ,  A61B3/0033 ,  A61B3/024 ,  A61B3/032 ,  A61B3/036 ,  A61B3/08 ,  A61H23/02 ,  A61H2201/0207 ,  A61H2201/10 ,  A61H2201/1604 ,  A61H2201/165 ,  A61H2201/501 ,  A61H2201/5043 ,  A61H2201/5048 ,  A61H2201/5058 ,  A61H2201/5092 ,  A61H2201/5097

摘要： A binocular viewer, a method of measuring and training vision that uses a binocular viewer and a vision measurement and training system that employs a computer to control the binocular viewer. In one embodiment, the binocular viewer has left and right display elements and comprises: (1) a variable focal depth optical subsystem located in an optical path between the display elements and a user when the user uses the binocular viewer and (2) a control input coupled to the left and right display elements and the variable focal depth optical subsystem and configured to receive control signals operable to place images on the left and right display elements and vary a focal depth of the variable focal depth optical subsystem. In another embodiment, the binocular viewer lacks the variable focal depth optical subsystem, but the images include at least one feature unique to one of the left and right display elements.

摘要翻译： 双眼观察者，使用双目观察者的测量和训练视觉的方法以及采用计算机来控制双目观察者的视觉测量和训练系统。 在一个实施例中，双目观察器具有左右显示元件，并且包括：（1）当用户使用双目观察者时，位于显示元件与用户之间的光路中的可变焦深光学子系统，以及（2）控制 输入，耦合到左和右显示元件和可变焦深度光学子系统，并且被配置为接收可操作以将图像放置在左显示元件和右显示元件上并改变可变焦深光学子系统的焦深的控制信号。 在另一个实施例中，双目观察器缺少可变焦深度光学子系统，但是图像包括左和右显示元件之一唯一的至少一个特征。

公开(公告)号：US08338208B2

公开(公告)日：2012-12-25

申请号：US12969910

申请日：2010-12-16

申请人： Edgar Rolando Zuniga-Ortiz ,  William R. Krenik

发明人： Edgar Rolando Zuniga-Ortiz ,  William R. Krenik

IPC分类号： H01L21/00

CPC分类号： B81B3/0021 ,  B81C1/00238 ,  B81C2203/0792 ,  H01L2224/16 ,  H01L2924/1461 ,  H01L2924/1815 ,  H01L2924/00

摘要： A MEMS may integrate movable MEMS parts, such as mechanical elements, flexible membranes, and sensors, with the low-cost device package, leaving the electronics and signal-processing parts in the integrated circuitry of the semiconductor chip. The package may be a leadframe-based plastic molded body having an opening through the thickness of the body. The movable part may be anchored in the body and extend at least partially across the opening. The chip may be flip-assembled to the leads to span across the foil, and may be separated from the foil by a gap. The leadframe may be a prefabricated piece part, or may be fabricated in a process flow with metal deposition on a sacrificial carrier and patterning of the metal layer. The resulting leadframe may be flat or may have an offset structure useful for stacked package-on-package devices.

摘要翻译： MEMS可以利用低成本器件封装集成可移动MEMS部件，例如机械元件，柔性膜和传感器，将电子器件和信号处理部件留在半导体芯片的集成电路中。 封装可以是具有通过主体厚度的开口的引线框架的塑料模制体。 可移动部分可以锚定在主体中并且至少部分地延伸穿过开口。 芯片可以被翻转组装到引线跨越箔片，并且可以通过间隙与箔片分离。 引线框架可以是预制件部件，或者可以以牺牲载体上的金属沉积和金属层的图案化的工艺流程制造。 所得到的引线框架可以是平坦的，或者可以具有对于堆叠的封装封装器件有用的偏移结构。

公开(公告)号：US6035320A

公开(公告)日：2000-03-07

申请号：US368679

申请日：1995-01-04

申请人： Sami Kiriaki ,  William R. Krenik

发明人： Sami Kiriaki ,  William R. Krenik

IPC分类号： H03M1/66 ,  H03H17/06 ,  G06G7/02 ,  G06F17/10

CPC分类号： H03H17/06

摘要： A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C.sub.1 -C.sub.5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

摘要翻译： 提供了一种新颖的有限脉冲响应滤波器（FIR）滤波器，其包括多个乘法器（14-22），多个复用器（24-32）和多个采样和保持电路（34-42）。 至少两个采样和保持电路输出信号（1-5）可以以循环方式复用到至少两个乘法器（14-22）。 乘法器可以接收作为第二输入的固定抽头系数信号（C1-C5），用于与复用的采样和保持电路输出信号（1-5）相乘。

公开(公告)号：US06021015A

公开(公告)日：2000-02-01

申请号：US861251

申请日：1997-05-21

申请人： Edward N. Jeffrey ,  William R. Krenik ,  David Cotton ,  Dennis V. Hahn ,  Shaibal Barua ,  Roy C. Jones, III

发明人： Edward N. Jeffrey ,  William R. Krenik ,  David Cotton ,  Dennis V. Hahn ,  Shaibal Barua ,  Roy C. Jones, III

IPC分类号： G11B19/20 ,  G11B19/28 ,  G11B21/08 ,  G11B21/10 ,  G11B25/04 ,  G11B33/12 ,  G11B15/18

CPC分类号： G11B33/121 ,  G11B19/20 ,  G11B19/28 ,  G11B21/083 ,  G11B21/10 ,  G11B25/043 ,  G11B33/122

摘要： A system for driving hard disk drive spindle and actuator motors is disclosed. The system comprises a spindle motor control circuit (120), a spindle motor power circuit (210), an actuator motor control circuit (110), and an actuator motor power circuit (210). The spindle motor control circuit (120) and the actuator motor control circuit (110) are formed on a first substrate (100). The spindle motor power circuit (210) and the actuator motor power circuit (220) are formed on a second substrate (200). The system also includes at least one disk (22) attached to a rotatable spindle (21), a spindle motor (400) for receiving and being energized by the spindle motor power signals, and for controlling the rotation of the spindle (21), a plurality of disk read heads (12) adjacent to the disks (22), and an actuator motor (300) for receiving and being energized by the actuator motor power signals, and for controlling the position of the disk read heads (12).

摘要翻译： 公开了一种用于驱动硬盘驱动器主轴和致动器电动机的系统。 该系统包括主轴电动机控制电路（120），主轴电动机功率电路（210），致动器电动机控制电路（110）和致动器电动机功率电路（210）。 主轴电动机控制电路（120）和致动器电动机控制电路（110）形成在第一基板（100）上。 主轴电动机功率电路（210）和致动器电动机功率电路（220）形成在第二衬底（200）上。 该系统还包括附接到可旋转主轴（21）的至少一个盘（22），用于由主轴电机功率信号接收和激励并用于控制主轴（21）的旋转的主轴电动机（400） 与盘（22）相邻的多个磁盘读取头（12）以及用于由致动器电机功率信号接收和激励并用于控制磁盘读取头（12）的位置的致动器马达（300）。

公开(公告)号：US5994926A

公开(公告)日：1999-11-30

申请号：US838300

申请日：1997-04-16

申请人： Patrick P. Siniscalchi ,  Davy H. Choi ,  William R. Krenik

发明人： Patrick P. Siniscalchi ,  Davy H. Choi ,  William R. Krenik

IPC分类号： H03F3/45 ,  H03G1/00 ,  H03K5/22

CPC分类号： H03G1/0023 ,  H03F3/45076

摘要： A programmably variable transconductance circuit (10) and method for varying its transconductance includes first and second current control input devices (16, 18), each having an input (17,19) to which a differential input voltage may be applied. A pair of current steering circuits (26, 28, 30, 32) are each connected in series with a respective one of the first and second current control devices (16, 18) for dividing respective currents in the first and second current control devices (16, 18) between a differential output current path (12, 14) and another current flow path, and a programmable voltage source (90) supplying V.sub.CONTROL is connected to control the current division by the current steering circuits (26, 28, 30, 32). The programmable voltage, V.sub.CONTROL, is provided by a programmable current control loop (90), which incorporates a master transconductance circuit, to establish a constant transconductance independently of temperature variations. A dynamically controllable resistance, such as an MOS transistor (24), or the like, is connected between the first and second current control input devices (16, 18), and a second voltage source (V.sub.GATE) is connected to the dynamically controllable resistance (24) to maintain the dynamically controllable resistance (24) at a constant value.

摘要翻译： 用于改变其跨导的可编程可变跨导电路（10）和方法包括第一和第二电流控制输入装置（16,18），每个具有可以施加差动输入电压的输入端（17,19）。 一对电流转向电路（26,28,30,32）各自与第一和第二电流控制装置（16,18）中的相应一个串联连接，用于分开第一和第二电流控制装置（ 16,28,30,30,40,30,40,30,40,30,40,30,40,30,40,30,40,40,30,40,30,40,40,40,40,43,40,40,40,40,40,40,40,40,40,40,40,40,40,62,62,62,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64 32）。 可编程电压VCONTROL由可编程电流控制回路（90）提供，可编程电流控制回路（90）包含主跨导电路，以独立于温度变化建立恒定跨导。 诸如MOS晶体管（24）等的动态可控电阻连接在第一和第二电流控制输入装置（16,18）之间，第二电压源（VGATE）连接到动态可控电阻 （24）以将所述动态可控电阻（24）保持在恒定值。

公开(公告)号：US5625209A

公开(公告)日：1997-04-29

申请号：US434816

申请日：1995-05-04

申请人： Mark Appleton ,  William R. Krenik

发明人： Mark Appleton ,  William R. Krenik

IPC分类号： G01N27/12 ,  H01L23/58

CPC分类号： G01N27/12 ,  Y10S148/035 ,  Y10S148/052

摘要： A biomedical sensor (20) is formed on a semiconductor substrate (22). Insulated dielectric layers (23, 24) are formed on the face and backside of the semiconductor substrate (22). Metal leads (26, 28) contact the substrate (22) through openings in the dielectric layer (23). The leads (26, 28) are also each connected to a set of interleaved longitudinal contact fingers (27, 29). A pair of contacts (30, 32) are formed on the opposite side of the substrate (22) from the contact figures (27, 29). A conductive biologic sample is placed over the interleaf fingers (27, 29), electrical measurements can be made through backside contacts (30, 32) so resistance measurements can be taken.

摘要翻译： 生物医学传感器（20）形成在半导体衬底（22）上。 绝缘电介质层（23,24）形成在半导体衬底（22）的表面和背面上。 金属引线（26,28）通过介电层（23）中的开口接触基板（22）。 引线（26,28）也各自连接到一组交错的纵向接触指（27,29）。 一对触点（30,32）形成在基板（22）的与接触图（27,29）相反的一侧上。 将导电生物样品放置在中间指状物（27,29）上，可以通过背侧触点（30,32）进行电气测量，因此可以进行电阻测量。