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    MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof
    1.
    发明授权
    MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof 失效
    具有p沟道MOS器件的MIS器件和具有LDD结构的n沟道MOS器件及其制造方法

    公开(公告)号：US5296401A

    公开(公告)日：1994-03-22

    申请号：US973250

    申请日：1992-11-09

    申请人： Katsuyoshi Mitsui ,  Shigeki Komori

    发明人： Katsuyoshi Mitsui ,  Shigeki Komori

    IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L29/78 ,  H01L21/70

    CPC分类号： H01L29/42376 ,  H01L21/823864 ,  H01L29/78 ,  H01L29/7836

    摘要： In a CMOS semiconductor device, a pMOS transistor and an nMOS transistor are formed on a single substrate. Each of the source/drain regions of the nMOS transistor and the pMOS transistor has LDD structure composed of a combination of a low concentration impurity region and a high concentration impurity region. The low concentration impurity region of the LDD structure of the pMOS transistor is formed in a self-align manner by ion implantation using a sidewall spacer with relatively thick film thickness. The low concentration impurity region of the LDD structure of the nMOS transistor is formed in a self-align manner by ion implantation using a relatively thin sidewall spacer as a mask. The sidewall spacer with thick film thickness of the pMOS transistor restrains that the channel between the source/drain regions is shortened due to thermal diffusion to cause punch through. As for the sidewall spacer of the nMOS transistor, its film thickness is selected to effectively restrain hot carrier effect in the vicinity of the drain and restrain degradation of current handling capability due to parasitic resistance to the minimum.

    摘要翻译： 在CMOS半导体器件中，在单个衬底上形成pMOS晶体管和nMOS晶体管。 nMOS晶体管和pMOS晶体管的源极/漏极区域中的每一个具有由低浓度杂质区域和高浓度杂质区域的组合构成的LDD结构。 pMOS晶体管的LDD结构的低浓度杂质区域通过使用具有相对厚的膜厚度的侧壁间隔件的离子注入以自对准的方式形成。 nMOS晶体管的LDD结构的低浓度杂质区域通过使用相对较薄的侧壁间隔物作为掩模的离子注入以自对准的方式形成。 具有pMOS晶体管的厚膜厚度的侧壁隔离层限制了源极/漏极区域之间的沟道由于热扩散而被缩短以引起穿通。 对于nMOS晶体管的侧壁间隔物，其膜厚度被选择为有效地抑制在漏极附近的热载流子效应，并且抑制由寄生电阻降到最小的电流处理能力的劣化。

    Display device
    2.
    发明授权
    Display device 有权
    显示设备

    公开(公告)号：US09196633B2

    公开(公告)日：2015-11-24

    申请号：US12556704

    申请日：2009-09-10

    申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

    发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

    IPC分类号： H01L33/00 ,  H01L27/12 ,  G02F1/1362 ,  H01L27/02 ,  H01L29/786

    CPC分类号： H01L27/124 ,  G02F1/136204 ,  G02F1/136286 ,  H01L27/0266 ,  H01L27/1225 ,  H01L29/7869

    摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

    摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅极绝缘层上的栅电极重叠的第一氧化物半导体层，以及第一布线层和第二布线层 其端部与第一氧化物半导体层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

    DISPLAY DEVICE
    4.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20100072470A1

    公开(公告)日：2010-03-25

    申请号：US12556695

    申请日：2009-09-10

    申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

    发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

    IPC分类号： H01L33/00

    CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

    摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

    摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅绝缘层上的栅电极重叠的第一氧化物半导体层，与沟道形成区重叠的沟道保护层 的第一氧化物半导体层，以及一对第一布线层和第二布线层，其端部与沟道保护层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    5.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 失效
    半导体器件和半导体器件的制造方法

    公开(公告)号：US20070026600A1

    公开(公告)日：2007-02-01

    申请号：US11381654

    申请日：2006-05-04

    申请人： Shigeki Komori

    发明人： Shigeki Komori

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/28518 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.

    摘要翻译： 提供了可以提高栅电极的所有区域被硅化的MOS晶体管的性能的技术。 将nMOS晶体管的栅极绝缘膜和栅电极依次层叠并形成在半导体基板上。 nMOS晶体管的源极/漏极区域形成在半导体衬底的上表面中。 在硅化栅电极的所有区域之后，源极/漏极区域被硅化。 因此，通过在栅极电极的硅化后硅化硅化源极/漏极区域，通过在栅电极的硅化处理进行热处理，硅化物不会在源极/漏极区域内固定。 因此，源极/漏极区域的电阻减小，结点泄漏可以减小。 结果，提高了nMOS晶体管的性能。

    Static semiconductor memory device
    7.
    发明授权
    Static semiconductor memory device 失效
    静态半导体存储器件

    公开(公告)号：US06747323B2

    公开(公告)日：2004-06-08

    申请号：US10330168

    申请日：2002-12-30

    申请人： Shigeki Komori

    发明人： Shigeki Komori

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A static semiconductor memory device capable of preventing soft errors is provided. The static semiconductor memory device includes: a silicon substrate having a p-type well region; a storage node; an n-type-low-concentration impurity region and a high-concentration impurity region formed in the surface of p-type well region and connected to storage node; and a p-type impurity region formed to have contact with high-concentration impurity region.

    摘要翻译： 提供了能够防止软错误的静态半导体存储器件。 静态半导体存储器件包括：具有p型阱区的硅衬底; 存储节点 连接到存储节点的p型阱区域的表面形成有n型低浓度杂质区域和高浓度杂质区域; 和形成为与高浓度杂质区接触的p型杂质区。

    Semiconductor device having first and second type field effect transistors separated by a barrier
    8.
    发明授权
    Semiconductor device having first and second type field effect transistors separated by a barrier 失效
    具有由屏障隔开的第一和第二类场效应晶体管的半导体器件

    公开(公告)号：US5138420A

    公开(公告)日：1992-08-11

    申请号：US608050

    申请日：1990-10-31

    申请人： Shigeki Komori ,  Katsuhiro Tsukamoto

    发明人： Shigeki Komori ,  Katsuhiro Tsukamoto

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0928 ,  Y10S257/929

    摘要： A complementary field effect element develops an intensified latch-up preventive property even if the distance between the emitters of parasitic transistors is short, and a method of producing the same are disclosed. The complementary field effect element includes a high concentration impurity layer (16) formed by ion implantation in the boundary region between a P-well (2) and an N-well (3) which are formed adjacent each other on the main surface of a semiconductor substrate (1). Therefore, carriers passing through the boundary region between the P-well (2) and the N-well (3) are decreased, so that even if the distance between the emitters (4, 5) of parasitic transistors is short, there is obtained an intensified latch-up preventive property.

    摘要翻译： 即使寄生晶体管的发射极之间的距离短，互补的场效应元件也产生增强的防闩锁特性，并且公开了其制造方法。 互补场效应元件包括在P阱（2）和N阱（3）之间的边界区域中通过离子注入形成的高浓度杂质层（16），它们彼此相邻地形成在 半导体衬底（1）。 因此，通过P阱（2）和N阱（3）之间的边界区域的载流子减少，使得即使寄生晶体管的发射极（4,5）之间的距离较短，也可获得 增强了防闩锁性能。

    Double diffusion metal-oxide-semiconductor device having shallow source and drain diffused regions
    9.
    发明授权
    Double diffusion metal-oxide-semiconductor device having shallow source and drain diffused regions 失效
    具有浅源极和漏极扩散区域的双扩散金属氧化物半导体器件

    公开(公告)号：US5045901A

    公开(公告)日：1991-09-03

    申请号：US577711

    申请日：1990-09-05

    申请人： Shigeki Komori ,  Katsuhiro Tsukamoto

    发明人： Shigeki Komori ,  Katsuhiro Tsukamoto

    IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66606 ,  H01L21/2257 ,  H01L21/28525 ,  H01L29/78

    摘要： A MOS transistor comprises source and drain impurity regions on a surface of a silicon substrate. The source and drain regions have a double diffusion structure including impurity regions of high concentration and impurity regions of low concentration surrounding the high-concentration impurity regions. Outgoing electrode layers of polysilicon are formed on surfaces of the source and drain impurity regions. A gate electrode is formed to partially extend over the outgoing electrode layers for the source and drain impurity regions. The source and drain impurity regions are formed by implanting impurities into the electrode layers and subsequently diffusing the impurities into the semiconductor substrate by thermal diffusion. Those processes of impurity implantation and thermal diffusion are effected after completion of the step of patterning the gate electrode. Since thermal diffusion of the impurity implantation for the source and drain regions occurs as a final heat treatment step in the process, the depth of the impurity implanted regions can be precisely controlled.