公开(公告)号：US06858376B2

公开(公告)日：2005-02-22

申请号：US10213413

申请日：2002-08-05

Applicant: Kay Lederer

Inventor： Kay Lederer

IPC: G03F7/40 ,  H01L21/027 ,  G03F7/26

CPC classification number: G03F7/40

Abstract: In a negative or positive photoresist layer structured with the aid of the customary lithography technique, the photoresist layer is heated briefly, in the region of the interface with the semiconductor substrate, to a temperature above the melting point to fuse the photoresist layer at the interface with the layer underneath on the semiconductor wafer.

Abstract translation: 在借助于常规光刻技术构造的负性或正性光致抗蚀剂层中，将光致抗蚀剂层在与半导体衬底的界面区域中短暂地加热至高于熔点的温度，以将界面处的光致抗蚀剂层熔合 其下面的层位于半导体晶片上。

公开(公告)号：US06797029B2

公开(公告)日：2004-09-28

申请号：US10330444

申请日：2002-12-27

Applicant: Kay Lederer ,  Steffen Hornig

Inventor： Kay Lederer ,  Steffen Hornig

IPC: B01D4600

CPC classification number: H01L21/67017 ,  Y10S55/18 ,  Y10S55/29 ,  Y10S55/46

Abstract: In a process facility for producing semiconductor wafers, a third physical unit is configured between two physical units that produce mini environments. The third physical unit has a laminar flow at right angles to the laminar flows of the two physical units and is operated with a slightly higher flow velocity. According to the Bernoulli equation, the static pressure in the third physical unit is therefore lower than in the surrounding two physical units. Advantageously, therefore, no contamination from the more highly loaded one of the two physical units passes over into the lesser loaded one of the two physical units.

Abstract translation: 在用于制造半导体晶片的处理设备中，第三物理单元被配置在产生迷你环境的两个物理单元之间。 第三物理单元具有与两个物理单元的层流成直角的层流，并且以略高的流速操作。 根据伯努利方程，第三物理单元中的静压力因此低于周围的两个物理单位。 因此，有利的是，来自两个物理单元中较高负载的物体的污染物不会传递到两个物理单元中的较小负载的物理单元中。

公开(公告)号：US08964188B2

公开(公告)日：2015-02-24

申请号：US13524210

申请日：2012-06-15

Applicant: Alfredo Calvimontes ,  Kay Lederer

Inventor： Alfredo Calvimontes ,  Kay Lederer

IPC: G01B9/02 ,  G01B11/24 ,  G01B11/06 ,  G01B11/30

CPC classification number: G01B11/0675 ,  G01B11/0625 ,  G01B11/24 ,  G01B11/30 ,  G01B2210/50

Abstract: The invention relates to the field of measurement technology and concerns a method and an apparatus, such as may be used, by way of example, in thin-layer technology for organic dielectric semi-conducting or conducting layers on substrates.The object of the invention is to indicate a method and an apparatus with which both the surface topography of the coating and that of the surface may be determined independently of one another, at the same position.The object is achieved by a method wherein the three-dimensional topography of the coating is determined using chromatic white light measurement and, subsequently, the thickness of the coating is determined using UV interferometry, and the surface topography of the coated surface is determined by a comparison with the overall dimensions of the coated surface.The object is further achieved by an apparatus wherein an apparatus for chromatic white light measurement and an apparatus for UV interferometry are disposed on a test bench.

Abstract translation: 本发明涉及测量技术领域，并且涉及一种方法和装置，例如可以用于例如用于衬底上的有机电介质半导体或导电层的薄层技术中的方法和装置。 本发明的目的是指示一种方法和装置，其可以在同一位置上彼此独立地确定涂层的表面形貌和表面的两个表面形貌。 该目的通过一种方法实现，其中使用彩色白光测量确定涂层的三维形貌，并且随后，使用UV干涉测量确定涂层的厚度，并且涂覆表面的表面形貌由 与涂层表面的整体尺寸进行比较。 该目的还通过一种其中将彩色白光测量装置和用于UV干涉测量的装置设置在测试台上的装置实现。

公开(公告)号：US20130110421A1

公开(公告)日：2013-05-02

申请号：US13696157

申请日：2011-05-06

Applicant: Kay Lederer

Inventor： Kay Lederer

IPC: G01R31/28 ,  G06F15/00 ,  G01N23/201

CPC classification number: G01R31/28 ,  G01N1/286 ,  G01N23/201 ,  G06F15/00 ,  H01J2237/28 ,  H01J2237/31745 ,  H01J2237/31749 ,  H01L22/12 ,  H01L22/24

Abstract: Performing an analysis of an electronic device sample by measuring a property at a plurality of points of said electronic device sample, and in advance of said analysis subjecting said plurality of points to at least one treatment that increases the difference in said property between at least two elements of said electronic device sample.

Abstract translation: 通过测量所述电子设备样本的多个点处的属性来进行对电子设备样本的分析，并且在所述分析之前，对所述多个点进行至少一个处理，所述处理增加所述属性的差异至少在两个 所述电子设备样品的元件。