公开(公告)号：US20130242431A1

公开(公告)日：2013-09-19

申请号：US13419283

申请日：2012-03-13

申请人： Kazuhiko Hosomi ,  Kimitoshi Eto ,  Mikito Sugiyama ,  Junichi Hashimoto ,  Kazue Kudo ,  Misuzu Kanai

发明人： Kazuhiko Hosomi ,  Kimitoshi Eto ,  Mikito Sugiyama ,  Junichi Hashimoto ,  Kazue Kudo ,  Misuzu Kanai

IPC分类号： G11B5/23 ,  G11B5/235

CPC分类号： G11B5/235 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic write head having a shield structure that provides both a leading shield and side shielding function. The magnetic shield is separated from the sides and leading edge of the write pole by a non-magnetic gap layer that has a non-uniform thickness. The non-magnetic gap layer is thicker near the leading edge and thinner at the trailing edge. This allows for increased side field gradient near the trailing edge of the write pole and decreased write field loss at the leading edge of the write pole.

摘要翻译： 具有提供前屏蔽和侧屏蔽功能的屏蔽结构的磁写头。 磁屏蔽通过非均匀厚度的非磁性间隙层与写磁极的侧边和前边缘分开。 非磁性间隙层在前缘附近较厚，在后缘较薄。 这允许在写入极的后沿附近增加的侧场梯度，并且在写入极的前沿减小写入场损耗。

公开(公告)号：US08570686B2

公开(公告)日：2013-10-29

申请号：US13419283

申请日：2012-03-13

申请人： Kazuhiko Hosomi ,  Kimitoshi Eto ,  Mikito Sugiyama ,  Junichi Hashimoto ,  Kazue Kudo ,  Misuzu Kanai

发明人： Kazuhiko Hosomi ,  Kimitoshi Eto ,  Mikito Sugiyama ,  Junichi Hashimoto ,  Kazue Kudo ,  Misuzu Kanai

IPC分类号： G11B5/33

CPC分类号： G11B5/235 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/315 ,  G11B5/3163

摘要： A magnetic write head having a shield structure that provides both a leading shield and side shielding function. The magnetic shield is separated from the sides and leading edge of the write pole by a non-magnetic gap layer that has a non-uniform thickness. The non-magnetic gap layer is thicker near the leading edge and thinner at the trailing edge. This allows for increased side field gradient near the trailing edge of the write pole and decreased write field loss at the leading edge of the write pole.

摘要翻译： 具有提供前屏蔽和侧屏蔽功能的屏蔽结构的磁写头。 磁屏蔽通过非均匀厚度的非磁性间隙层与写磁极的侧边和前边缘分开。 非磁性间隙层在前缘附近较厚，在后缘较薄。 这允许在写入极的后沿附近增加的侧场梯度，并且在写入极的前沿减小写入场损耗。

公开(公告)号：US06576946B1

公开(公告)日：2003-06-10

申请号：US09356705

申请日：1999-07-20

申请人： Misuzu Kanai ,  Yuzuru Ohji ,  Takuya Fukuda ,  Shinpei Iijima ,  Ryouichi Furukawa ,  Yasuhiro Sugawara ,  Hideharu Yahata

发明人： Misuzu Kanai ,  Yuzuru Ohji ,  Takuya Fukuda ,  Shinpei Iijima ,  Ryouichi Furukawa ,  Yasuhiro Sugawara ,  Hideharu Yahata

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10814

摘要： Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

摘要翻译： 电容器沿着位线的方向在多个存储单元上被拉伸，以有效地利用相邻单元之间的空间。 此外，通过采用自匹配技术来形成每个电容器的立方结构，可以更有效地利用结构。 结果，尽管制造技术受到限制，但是可以确保足够的电容器电容，并且可以确保伴随高精度集成的存储单元的收缩区域中的单元之间的足够的空间以及半导体的小型化 设备。

公开(公告)号：US06627497B2

公开(公告)日：2003-09-30

申请号：US10162192

申请日：2002-06-05

申请人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

发明人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

IPC分类号： H01L218242

CPC分类号： H01L21/31604 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/56 ,  H01L28/60 ,  H01L28/65

摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

公开(公告)号：US06544834B1

公开(公告)日：2003-04-08

申请号：US09720002

申请日：2000-12-19

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。

公开(公告)号：US06583463B1

公开(公告)日：2003-06-24

申请号：US09172196

申请日：1998-10-14

申请人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

发明人： Naruhiko Nakanishi ,  Nobuyoshi Kobayashi ,  Yuzuru Ohji ,  Sinpei Iijima ,  Yasuhiro Sugawara ,  Misuzu Kanai

IPC分类号： H01L27108

CPC分类号： H01L21/31604 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02337 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10882 ,  H01L27/10894 ,  H01L28/56 ,  H01L28/60 ,  H01L28/65

摘要： A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

摘要翻译： 一种半导体集成电路器件，包括存储单元，该存储单元包括形成在半导体衬底1的主表面上的存储单元选择MISFET Qs和与所述存储单元选择MISFET Qs串联连接的信息存储电容器C， 电极54，电容器绝缘体58和上电极59，其中下电极54由含有二氧化钌（RuO 2）作为主要成分的导电材料制成，并且电容器绝缘体58由结晶的五氧化二钽制成。 因此，可以确保256Mbits DRAM的存储单元或后一代的DRAM的存储单元所需的电容。

公开(公告)号：US20080273274A1

公开(公告)日：2008-11-06

申请号：US12012864

申请日：2008-02-05

申请人： Shuichi Kojima ,  Goichi Kojima ,  Misuzu Kanai ,  Ysaunari Tajima ,  Satoru Okamoto

发明人： Shuichi Kojima ,  Goichi Kojima ,  Misuzu Kanai ,  Ysaunari Tajima ,  Satoru Okamoto

IPC分类号： G11B5/33

CPC分类号： G11B5/3909 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3906 ,  G11B2005/3996

摘要： Embodiments of the present invention help to suppress etching damage to a non-magnetic intermediate layer in manufacturing steps of a reproducing head. In one embodiment, a reproducing head has two junction insulating films between side ends of magnetoresistive sensor and hard bias films at both left and right of a track width direction of the magnetoresistive sensor. The reproducing head has first junction insulating films in addition to second junction insulating films. The first junction insulating film suppresses etching damage to the non-magnetic intermediate layer in the manufacturing steps of the reproducing head

摘要翻译： 本发明的实施例有助于在再现头的制造步骤中抑制非磁性中间层的蚀刻损伤。 在一个实施例中，再现头在磁阻传感器的侧端和磁阻传感器的磁道宽度方向左右两侧的硬偏置膜之间具有两个结绝缘膜。 再现头除了第二结绝缘膜之外还具有第一结绝缘膜。 在再现头的制造步骤中，第一结绝缘膜抑制对非磁性中间层的蚀刻损伤

公开(公告)号：US06713343B2

公开(公告)日：2004-03-30

申请号：US10388618

申请日：2003-03-17

申请人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

发明人： Yasuhiro Sugawara ,  Shinpei Iijima ,  Yuzuru Oji ,  Naruhiko Nakanishi ,  Misuzu Kanai ,  Masahiko Hiratani

IPC分类号： H01L218242

CPC分类号： H01L27/1085 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02356 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L28/40

摘要： An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

摘要翻译： 集成半导体器件具有改进的可靠性并且适于更高的集成度，而不减少每个信息存储电容元件的累积电荷。 半导体器件具有DRAM，其具有存储单元，每个DRAM包括与形成在半导体衬底1的主表面上的存储单元选择MISFET Qs串联连接的信息存储电容元件C，具有下电极54，电容绝缘 膜58和上电极59.下电极54由在特定平面轴承（例如（002））面取向的钌膜制成，并且电容绝缘膜58由通过热处理得到的多晶钽膜制成 含有沉淀状态的结晶用氧化钽晶体的无定形氧化钽膜。