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    Microprogram controller in which instruction following conditional branch instruction is selectively converted to a NOP instruction
    1.
    发明授权
    Microprogram controller in which instruction following conditional branch instruction is selectively converted to a NOP instruction 失效
    微程序控制器，其中指令跟随条件分支指令被选择性地转换为NOP指令

    公开(公告)号：US4773002A

    公开(公告)日：1988-09-20

    申请号：US865388

    申请日：1986-05-21

    申请人： Kazuhiko Iwasaki ,  Noboru Yamaguchi ,  Tsuneo Funabashi ,  Junichi Tatezaki ,  Takanori Shimura

    发明人： Kazuhiko Iwasaki ,  Noboru Yamaguchi ,  Tsuneo Funabashi ,  Junichi Tatezaki ,  Takanori Shimura

    IPC分类号： G06F9/28 ,  G06F9/22 ,  G06F9/26 ,  G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/264

    摘要： In a microprogram controller by pipeline control which includes a memory for storing a microprogram and a program counter for representing the address of the memory, a microprogram controller includes means for judging whether or not a branch condition of a branch microinstruction is satisfied and means for converting the microinstruction fetched from the memory to a NOP (No Operation) microinstruction from the output of the next step of the memory till the outputs after a plurality of steps by the affirmation output of the judging means. When the affirmation output is obtained from the judging means, part of the memory output is loaded into the program counter and when the negation output is obtained, a value as the sum of a current value plus 1 is loaded into the program counter.

    摘要翻译： 在通过流水线控制的微程序控制器中，包括用于存储微程序的存储器和用于表示存储器的地址的程序计数器，微程序控制器包括用于判断分支微指令的分支条件是否满足的装置和用于转换的装置 通过判断装置的肯定输出，从存储器的下一个步骤的输出，从存储器中取出的微指令到NOP（无操作）微指令，直到多个步骤之后的输出。 当从判断装置获得确认输出时，存储器输出的一部分被加载到程序计数器中，并且当获得否定输出时，将作为当前值加1的和的值加载到程序计数器中。

    Decoding method and apparatus for cyclic codes
    2.
    发明授权
    Decoding method and apparatus for cyclic codes 失效
    用于循环码的解码方法和装置

    公开(公告)号：US4677623A

    公开(公告)日：1987-06-30

    申请号：US669423

    申请日：1984-11-08

    申请人： Kazuhiko Iwasaki ,  Junichi Tatezaki ,  Tsuneo Funabashi

    发明人： Kazuhiko Iwasaki ,  Junichi Tatezaki ,  Tsuneo Funabashi

    IPC分类号： H03M1/00 ,  H03M13/17 ,  G06F11/10

    CPC分类号： H03M13/17

    摘要： In an apparatus for decoding cyclic codes generated by a generator polynomial ##EQU1## (where P.sub.i (x) is a m.sub.i -order irreducible polynomial) including 0-th to l-th feedback shift registers corresponding to the terms (x.sup.c +1) and P.sub.i (x), a coincidence circuit for detecting coincidence of a predetermined number of low order bits of said 0-th to l-th feedback shift registers and all-zero conditions of a high order bits, the predetermined number being a minimum one of numbers of bits (c, m.sub.1, m.sub.2, . . . m.sub.l) of the feedback shift register, the 0-th feedback shift register having an output terminal thereof connected to an input terminal thereof, and the 1st to l-th feedback shift registers each having an output terminal thereof connected to an input terminal thereof and having exclusive OR gates inserted between stages determined by the associated simple polynomial, exclusive OR gates each receiving the output of the associated feedback shift register as one input thereto; a method for decoding the cyclic code for correcting a burst error by shifting the 0-th to l-th feedback shift registers until the coincidence circuit detects the coincidence, comprising the steps of; shifting at least one of said 0-th to l-th feedback shift registers a predetermined number of times; and simultaneously shifting the 0-th to l-th feedback shift registers after the predetermined number of shifting until the coincidence circuit detects the coincidence.

    摘要翻译： 在用于解码由生成多项式（其中Pi（x）是mi阶不可约数多项式）生成的循环码的装置，包括对应于项（xc + 1）的第0至第1反馈移位寄存器和 Pi（x），用于检测所述第0至第1反馈移位寄存器的预定数量的低位比特和高位比特的全零条件的符合电路，所述预定数是 反馈移位寄存器的位数（c，m1，m2，...），第0反馈移位寄存器，其输出端连接到其输入端，第1至第1反馈移位寄存器 每个具有连接到其输入端的输出端，并且具有插入在由相关联的简单多项式确定的级之间的异或门，每个异或门接收相关联的反馈移位寄存器的输出作为其一个输入; 一种用于通过移位第0到第1反馈移位寄存器来纠正突发错误的循环码的解码方法，直到符合电路检测到重合为止，包括以下步骤： 将所述第0到第1反馈移位寄存器中的至少一个移位预定次数; 并且在预定的移位数之后同时移动第0到第1反馈移位寄存器，直到符合电路检测到一致。

    Data processing system with an enhanced communication control system
    3.
    发明授权
    Data processing system with an enhanced communication control system 失效
    具有增强型通信控制系统的数据处理系统

    公开(公告)号：US4674037A

    公开(公告)日：1987-06-16

    申请号：US690609

    申请日：1985-01-11

    申请人： Tsuneo Funabashi ,  Kazuhiko Iwasaki ,  Noboru Yamaguchi ,  Takanori Shimura ,  Junichi Tatezaki

    发明人： Tsuneo Funabashi ,  Kazuhiko Iwasaki ,  Noboru Yamaguchi ,  Takanori Shimura ,  Junichi Tatezaki

    IPC分类号： H04L29/02 ,  G06F13/00 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177

    CPC分类号： G06F15/167

    摘要： A data buffer is connected to the first and second processor and the first processor sends a start signal to the second processor, which responds to the start signal by reading data from a data source, such as an input/output device, and then writes the read out data into the data buffer. After conclusion of the writing operation, the second processor sends an end signal to the first processor which is admitted to start sending data stored in the buffer to a host processor after receipt of the start signal. The start signal and the end signal are provided to the second processor and the first processor respectively, after passing through a synchronizing circuit.

    摘要翻译： 数据缓冲器连接到第一处理器和第二处理器，第一处理器向第二处理器发送起始信号，第二处理器通过从数据源（例如输入/输出设备）读取数据来响应起始信号，然后写入 读出数据到数据缓冲区。 在写入操作结束之后，第二处理器向接收到开始信号的主处理器发送结束信号给第一处理器，该第一处理器被允许开始向主处理器发送存储在缓冲器中的数据。 开始信号和结束信号分别在通过同步电路之后提供给第二处理器和第一处理器。

    Information transmitting/processing system
    8.
    发明授权
    Information transmitting/processing system 失效
    信息发送/处理系统

    公开(公告)号：US5619361A

    公开(公告)日：1997-04-08

    申请号：US182657

    申请日：1994-01-18

    申请人： Yasuhiro Sagesaka ,  Yoshifumi Kawamura ,  Junichi Tatezaki ,  Hideo Wada ,  Isao Kodama ,  Atsushi Ogane

    发明人： Yasuhiro Sagesaka ,  Yoshifumi Kawamura ,  Junichi Tatezaki ,  Hideo Wada ,  Isao Kodama ,  Atsushi Ogane

    IPC分类号： H04B10/2507 ,  H04B10/00 ,  H04B10/11 ,  H04B10/116 ,  H04B10/272 ,  H04B10/524 ,  G05B23/02

    CPC分类号： H04B10/1149

    摘要： A base station (5) comprises a base transmitter (6) for transmitting information optically to a plurality of portable stations (1 to 4) at such a predetermined time interval as is designated by portable station designating information. Each of the portable stations (1 to 4) comprises a potable transmitter (7) for transmitting information optically to the base station (5) in response to the transmission, which is designated by the portable station designating information coming from said base station (5), and within the range of the aforementioned time interval immediately after said transmission. Transmissions (ACK1 to ACK4) from the mating portable stations to the base station are individually inserted between the interval periods of the transmissions (REQ1 to REQ4) from the base station (5) to the portable stations (1 to 4) so that the single base station performs optical communications with the plurality of portable stations in a half-duplex time sharing manner.

    摘要翻译： 基站（5）包括用于以由便携式站指定信息指定的预定时间间隔向多个便携式站（1至4）光学发送信息的基站发射机（6）。 每个便携式站（1至4）包括用于响应于由便携式站指定来自所述基站（5）的信息指定的传输而向基站（5）光学发送信息的便携式发射机（7） ），并且在所述发送之后的上述时间间隔的范围内。 在从基站（5）到便携式站（1至4）的传输的间隔周期（REQ1至REQ4）之间单独插入从配对的便携式站到基站的传输（ACK1至ACK4），使得单个 基站以半双工时分方式与多个便携站进行光通信。