公开(公告)号：US08557711B2

公开(公告)日：2013-10-15

申请号：US12352020

申请日：2009-01-12

申请人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

发明人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

IPC分类号： H01L21/306 ,  B44C1/22

CPC分类号： C23F1/20 ,  H01L21/32134

摘要： The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.

摘要翻译： 本发明的目的在于提供一种能够以可控制的方式蚀刻金属膜，形成期望的定形锥形形状的蚀刻溶液组合物，并获得光滑表面而不引起蚀刻溶液渗出痕迹。 所述问题已经通过本发明来解决，本发明是用于蚀刻含有一种或多种选自烷基硫酸盐或全氟链烯基苯基醚磺酸的表面活性剂的金属膜的蚀刻溶液组合物及其盐。

公开(公告)号：US20050136672A1

公开(公告)日：2005-06-23

申请号：US11001737

申请日：2004-12-02

申请人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

发明人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

IPC分类号： C09K13/06 ,  C09K13/08 ,  C23F1/16 ,  C23F1/20 ,  H01L21/302 ,  H01L21/308 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/461

CPC分类号： C23F1/20 ,  H01L21/32134

摘要： The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.

摘要翻译： 本发明的目的在于提供一种能够以可控制的方式蚀刻金属膜，形成期望的定形锥形形状的蚀刻溶液组合物，并获得光滑表面而不引起蚀刻溶液渗出痕迹。 所述问题已经通过本发明来解决，本发明是用于蚀刻含有一种或多种选自烷基硫酸盐或全氟链烯基苯基醚磺酸的表面活性剂的金属膜的蚀刻溶液组合物及其盐。

公开(公告)号：US20090124091A1

公开(公告)日：2009-05-14

申请号：US12352020

申请日：2009-01-12

申请人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

发明人： Kazuhiro Fujikawa ,  Tsuguhiro Tago

IPC分类号： H01L21/306 ,  B44C1/22

CPC分类号： C23F1/20 ,  H01L21/32134

摘要： The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.

摘要翻译： 本发明的目的在于提供一种能够以可控制的方式蚀刻金属膜，形成期望的定形锥形形状的蚀刻溶液组合物，并获得光滑表面而不引起蚀刻溶液渗出痕迹。 所述问题已经通过本发明来解决，本发明是用于蚀刻含有一种或多种选自烷基硫酸盐或全氟链烯基苯基醚磺酸的表面活性剂的金属膜的蚀刻溶液组合物及其盐。

公开(公告)号：US09017856B2

公开(公告)日：2015-04-28

申请号：US13819172

申请日：2011-08-23

申请人： Suetsugu Kanai ,  Kazuhiro Fujikawa

发明人： Suetsugu Kanai ,  Kazuhiro Fujikawa

IPC分类号： H01M2/34 ,  H01M2/14 ,  H01M2/18 ,  H01M2/26 ,  H01M10/0525 ,  H01M10/0585 ,  H01M6/46 ,  H01M10/04

CPC分类号： H01M2/347 ,  H01M2/14 ,  H01M2/18 ,  H01M2/266 ,  H01M6/46 ,  H01M10/0413 ,  H01M10/0427 ,  H01M10/0436 ,  H01M10/0463 ,  H01M10/0525 ,  H01M10/0585 ,  Y02E60/122

摘要： The stacked battery includes a negative electrode (46) and a positive electrode (41). The negative electrode has a negative electrode main portion (50) and a negative electrode lead (52). The positive electrode has a positive electrode main portion (45) and a positive electrode lead (51). The negative electrode main portion and the positive electrode main portion are stacked in a thickness direction with the negative electrode lead and the positive electrode lead extending in different directions as viewed from above. The positive electrode lead is fixed to a positive electrode case. In the positive electrode lead, a break place (X) is provided outside the negative electrode main portion as viewed from above when the negative electrode and the positive electrode are placed on top of each other. The break place (X) is broken when a shock is applied to the electrodes.

摘要翻译： 叠层电池包括负极（46）和正极（41）。 负极具有负极主体部（50）和负极引线（52）。 正极具有正极主体部（45）和正极引线（51）。 负极主体部分和正极主体部分沿着厚度方向堆叠，负极引线和正极引线沿着从上方观察的不同方向延伸。 正极引线固定在正极壳体上。 在正极引线中，当负极和正极彼此顶部放置时，从负极电极主体的外侧设置断开位置（X）。 当对电极施加冲击时，断点（X）断裂。

公开(公告)号：US07750377B2

公开(公告)日：2010-07-06

申请号：US11770414

申请日：2007-06-28

申请人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

发明人： Takashi Hoshino ,  Shin Harada ,  Kazuhiro Fujikawa ,  Satoshi Hatsukawa ,  Kenichi Hirotsu

IPC分类号： H01L29/80

CPC分类号： H01L29/66068 ,  H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66909 ,  H01L29/8083

摘要： A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.

摘要翻译： 根据本发明的垂直JFET 1a具有n +型漏极半导体部分2，n型漂移半导体部分3，p +型栅极半导体部分4，n型沟道半导体部分5，n +型源半导体部分 7和p +型栅极半导体部分8.n型漂移半导体部分3放置在n +型漏极半导体部分2的主表面上，并且具有在与主体相交的方向上延伸的第一至第四区域3a至3d 表面。 p +型栅极半导体部分4放置在n型漂移半导体部分3的第一至第三区域3a至3c上.n型沟道半导体部分5沿着p +型栅极半导体部分4放置并且电连接 到n型漂移半导体部分3的第四区域3d。

公开(公告)号：US20100102331A1

公开(公告)日：2010-04-29

申请号：US12444537

申请日：2007-08-13

申请人： Kazuhiro Fujikawa ,  Hideto Tamaso

发明人： Kazuhiro Fujikawa ,  Hideto Tamaso

IPC分类号： H01L29/24 ,  H01L23/532 ,  H01L21/283

CPC分类号： H01L21/0485 ,  H01L29/45 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.

摘要翻译： 提供了包含Si和Ni的SiC半导体的欧姆电极或者除了Si和Ni之外还含有Au或Pt的用于SiC半导体的欧姆电极。 此外，提供了一种制造用于SiC半导体的欧姆电极的方法，包括用于SiC半导体的欧姆电极的半导体器件和制造该半导体器件的方法。

公开(公告)号：US07671388B2

公开(公告)日：2010-03-02

申请号：US12552212

申请日：2009-09-01

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/78

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

公开(公告)号：US20090152566A1

公开(公告)日：2009-06-18

申请号：US10583501

申请日：2005-09-08

申请人： Kazuhiro Fujikawa ,  Shin Harada

发明人： Kazuhiro Fujikawa ,  Shin Harada

IPC分类号： H01L29/80

CPC分类号： H01L29/808 ,  H01L29/1608 ,  H01L29/8083

摘要： A junction field-effect transistor comprises an n-type semiconductor layer having a channel region, a buffer layer formed on the channel region and a p+ region formed on the buffer layer. The concentration of electrons in the buffer layer is lower than the concentration of electrons in the semiconductor layer. The concentration of electrons in the buffer layer is preferably not more than one tenth of the concentration of electrons in the semiconductor layer. Thus, the threshold voltage can be easily controlled, and saturation current density of a channel can be easily controlled.

摘要翻译： 结型场效应晶体管包括具有沟道区的n型半导体层，形成在沟道区上的缓冲层和形成在缓冲层上的p +区。 缓冲层中的电子浓度低于半导体层中电子的浓度。 缓冲层中的电子浓度优选不超过半导体层中的电子浓度的十分之一。 因此，可以容易地控制阈值电压，并且可以容易地控制通道的饱和电流密度。

公开(公告)号：US07420232B2

公开(公告)日：2008-09-02

申请号：US11402701

申请日：2006-04-11

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US08643065B2

公开(公告)日：2014-02-04

申请号：US12919992

申请日：2009-12-11

申请人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

发明人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

IPC分类号： H01L29/80

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。