公开(公告)号：US4812735A

公开(公告)日：1989-03-14

申请号：US138798

申请日：1987-12-28

申请人： Kazuhiro Sawada ,  Takayasu Sakurai

发明人： Kazuhiro Sawada ,  Takayasu Sakurai

IPC分类号： G05F3/24 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  G05F3/30

CPC分类号： G05F3/247

摘要： This invention provides an intermediate potential generating circuit comprising a load element of which one end is connected to a first potential supply source, a first transistor of a first conductivity type of which one end and the gate thereof are connected to the other end of the load element, a second transistor of a second conductivity type of which one end is connected to the other end of the first transistor, and the gate and the other end thereof are connected together, a constant-voltage means connected between the other end of the second transistor and a second potential supply source for causing a specific voltage drop between the ends of the contant-voltage means, a third transistor of the first conductivity type of which one end is connected to the first potential supply source, the gate is connected to a node between the load element and the first transistor, and the other end thereof is connected to an output terminal, and a fourth transistor of the second conductivity type which is connected between the output terminal and the second supply source and of which the gate is connected to a node between the second transistor and the constant-voltage means.

公开(公告)号：US5153699A

公开(公告)日：1992-10-06

申请号：US717177

申请日：1991-06-18

申请人： Tsukasa Shirotori ,  Kazuhiro Sawada ,  Takayasu Sakurai

发明人： Tsukasa Shirotori ,  Kazuhiro Sawada ,  Takayasu Sakurai

IPC分类号： H01L21/76 ,  G11C11/401 ,  H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/118

CPC分类号： H01L23/528 ,  H01L27/10805 ,  H01L27/118 ,  H01L27/105 ,  H01L2924/0002

摘要： A semiconductor device comprises a logic circuit and a memory including a timing signal generator circuit, both formed in a substrate, and a wiring connecting the logic circuit to the memory, in which a diffusion layers connected to receive a predetermined potential is located under an area of the wiring situated between the logic circuit and the memory whereby it is possible to alleviate an effect from minority carriers and a substrate potential variation.

摘要翻译： 半导体器件包括逻辑电路和存储器，其包括形成在衬底中的定时信号发生器电路和将逻辑电路连接到存储器的布线，其中连接以接收预定电位的扩散层位于区域 位于逻辑电路和存储器之间的布线，由此可以减轻少数载流子的影响和衬底电位变化。

公开(公告)号：US4939695A

公开(公告)日：1990-07-03

申请号：US268927

申请日：1988-11-09

申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Kazutaka Nogami ,  Hisashi Ueno

发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Kazutaka Nogami ,  Hisashi Ueno

IPC分类号： G11C11/403 ,  G11C11/406

CPC分类号： G11C11/406

摘要： A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

公开(公告)号：US4984208A

公开(公告)日：1991-01-08

申请号：US364529

申请日：1989-06-12

申请人： Kazuhiro Sawada ,  Takayasu Sakurai ,  Kazutaka Nogami

发明人： Kazuhiro Sawada ,  Takayasu Sakurai ,  Kazutaka Nogami

IPC分类号： G11C11/403 ,  G11C11/406

CPC分类号： G11C11/406

摘要： A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.

摘要翻译： 动态读/写存储器，其中在读/写周期内执行刷新以使写恢复时间不延长。 对应于当前地址的字线在写入周期内连续地进行操作。 当写入操作完成时，字线被操作，从而启动刷新。 字线只能在读取周期的给定时间段内运行。

公开(公告)号：US4587638A

公开(公告)日：1986-05-06

申请号：US630115

申请日：1984-07-12

申请人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

发明人： Mitsuo Isobe ,  Takayasu Sakurai ,  Kazuhiro Sawada ,  Tetsuya Iizuka ,  Takayuki Ohtani ,  Akira Aono

IPC分类号： G11C29/00 ,  G11C7/02

CPC分类号： G11C29/84 ,  G11C29/832

摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.

摘要翻译： 在根据本发明的半导体存储器件中，当存储单元中存在缺陷部分时，这些存储单元被冗余存储单元替换。 当在存储单元中发现有缺陷的部分时，与具有缺陷部分的存储单元相对应的熔丝元件被切断。 连接到具有缺陷部分的存储单元的选择线的电压由电阻器保持在L电平。 因此，不选择具有缺陷部分的存储单元。

公开(公告)号：US4827453A

公开(公告)日：1989-05-02

申请号：US127261

申请日：1987-12-01

申请人： Kazuhiro Sawada ,  Takayasu Sakurai

发明人： Kazuhiro Sawada ,  Takayasu Sakurai

IPC分类号： G11C11/407 ,  G11C7/22 ,  G11C8/18 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4076 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/18

摘要： A semiconductor memory control circuit separates an externally input operation activation signal from an operation activation signal which is transferred inside a memory, and activates the internal operation activation signal only for a predetermined period of time. This predetermined period is determined in accordance with the cycle time required to achieve refreshment of a memory cell after the external operation activation signal is activated. Thereafter, even if the external operation activation signal is in an activated state, the internal operation activation signal is inactivated. When the internal operation activation signal is in the activated state and the external operation activation signal is inactivated, the internal operation activation signal is inactivated, in accordance with activation of the external operation activation signal.

公开(公告)号：US4757217A

公开(公告)日：1988-07-12

申请号：US11882

申请日：1987-02-06

申请人： Kazuhiro Sawada ,  Takayasu Sakurai ,  Kazutaka Nogami

发明人： Kazuhiro Sawada ,  Takayasu Sakurai ,  Kazutaka Nogami

IPC分类号： G11C11/403 ,  G11C11/406 ,  H03K3/356

CPC分类号： G11C11/406

摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

公开(公告)号：US08618870B2

公开(公告)日：2013-12-31

申请号：US13377009

申请日：2010-06-11

申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

IPC分类号： G05F1/10

CPC分类号： G11C11/413

摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

公开(公告)号：US20060039182A1

公开(公告)日：2006-02-23

申请号：US11205466

申请日：2005-08-16

申请人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

发明人： Takayasu Sakurai ,  Hiroshi Kawaguchi ,  Robert Fayez

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.

摘要翻译： 存储单元阵列包括以矩阵形式布置的多个存储单元。 字线和电源线分别连接到布置在每一行中的多个存储单元。 电源线/字线控制电路连接到每个字线和每个电源线。 在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。 另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压 供电线路为低电压。

公开(公告)号：US5434517A

公开(公告)日：1995-07-18

申请号：US215174

申请日：1994-03-21

申请人： Hiroyuki Hara ,  Takayasu Sakurai

发明人： Hiroyuki Hara ,  Takayasu Sakurai

IPC分类号： H03K19/08 ,  H03K19/018 ,  H03K19/082 ,  H03K19/086

CPC分类号： H03K19/01812 ,  H03K19/0826

摘要： An ECL output buffer circuit is constituted by an output buffer circuit main portion and its control circuit. In the output buffer circuit main portion, an output from a differential switch is input to the base of a bipolar transistor (emitter follower). The emitter of the bipolar transistor is connected to an output terminal. A ground potential is applied to the collector of the bipolar transistor. One end of the channel conductive path of a MOS transistor is connected to the base of the bipolar transistor. The other end of the channel conductive path is connected to a power-supply terminal via a constant-current source. The control circuit controls the ON/OFF operation of the MOS transistor and the output level of the bipolar transistor. When the output buffer circuit main portion is to be set in a standby state, the control circuit performs control to set the MOS transistor in an ON state and set the output of the bipolar transistor at low level.

摘要翻译： ECL输出缓冲电路由输出缓冲电路主要部分及其控制电路构成。 在输出缓冲电路主要部分中，差分开关的输出被输入到双极晶体管（射极跟随器）的基极。 双极晶体管的发射极连接到输出端子。 接地电位施加到双极晶体管的集电极。 MOS晶体管的沟道导电路径的一端连接到双极晶体管的基极。 通道导电路径的另一端经由恒流源与电源端子连接。 控制电路控制MOS晶体管的ON / OFF操作和双极晶体管的输出电平。 当输出缓冲器电路主要部分被设置在待机状态时，控制电路进行控制以将MOS晶体管设置在导通状态，并将双极晶体管的输出设置为低电平。