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    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit
    1.
    发明授权
    Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
    锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器

    公开(公告)号：US08618870B2

    公开(公告)日：2013-12-31

    申请号：US13377009

    申请日：2010-06-11

    申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    IPC分类号： G05F1/10

    CPC分类号： G11C11/413

    摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

    摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

    VOLTAGE CHARACTERISTIC REGULATING METHOD OF LATCH CIRCUIT, VOLTAGE CHARACTERISTIC REGULATING METHOD OF SEMICONDUCTOR DEVICE, AND VOLTAGE CHARACTERISTIC REGULATOR OF LATCH CIRCUIT
    2.
    发明申请
    VOLTAGE CHARACTERISTIC REGULATING METHOD OF LATCH CIRCUIT, VOLTAGE CHARACTERISTIC REGULATING METHOD OF SEMICONDUCTOR DEVICE, AND VOLTAGE CHARACTERISTIC REGULATOR OF LATCH CIRCUIT 失效
    电压电路的特性调节方法，半导体器件的电压特性调节方法和电压电路特性调节器

    公开(公告)号：US20120182064A1

    公开(公告)日：2012-07-19

    申请号：US13377009

    申请日：2010-06-11

    申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Makoto Suzuki

    IPC分类号： G05F1/10

    CPC分类号： G11C11/413

    摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.

    摘要翻译： 电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对 导通晶体管的栅极和半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。 该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善 。

    Semiconductor integrated circuit
    3.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06529042B1

    公开(公告)日：2003-03-04

    申请号：US09548658

    申请日：2000-04-13

    申请人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Takashi Inukai

    发明人： Toshiro Hiramoto ,  Takayasu Sakurai ,  Takashi Inukai

    IPC分类号： H03K19094

    CPC分类号： H03K19/0016

    摘要： A semiconductor integrated circuit of the present invention has a CMOS circuit 1 composed of a first MOSFET and a switch 2 composed of a second MOSFET which are connected in series. Then, a circuit-driving voltage and a switch-driving voltage are applied independently to the CMOS circuit 1 and the switch 2. The switch-driving voltage is larger than the circuit-driving voltage.

    摘要翻译： 本发明的半导体集成电路具有由第一MOSFET和由串联连接的第二MOSFET构成的开关2构成的CMOS电路1。 然后，电路驱动电压和开关驱动电压独立地施加到CMOS电路1和开关2.开关驱动电压大于电路驱动电压。

    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals
    4.
    发明授权
    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
    半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作

    公开(公告)号：US5457412A

    公开(公告)日：1995-10-10

    申请号：US149935

    申请日：1993-11-10

    申请人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    发明人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    IPC分类号： G11C11/413 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/0175 ,  H03K19/08

    CPC分类号： H03K19/017527

    摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

    摘要翻译： 提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。 输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和 电路。 该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。 由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5854497A

    公开(公告)日：1998-12-29

    申请号：US773312

    申请日：1996-12-24

    申请人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    发明人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction.More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

    摘要翻译： 一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域 沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。 更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5594270A

    公开(公告)日：1997-01-14

    申请号：US314775

    申请日：1994-09-29

    申请人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    发明人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  G11C11/00

    CPC分类号： G11C11/412 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

    摘要翻译： 一种半导体存储器件，具有多个存储单元，每个存储单元包括彼此交叉耦合并且布置在沿列方向延伸的多个字线和沿行方向延伸的多个互补数据线对的交点处的两个CMOS反相器; 其中沿着列方向布置的存储单元的p沟道型负载MISFET形成在n型阱区域的字线延伸方向的主表面上，p沟道型负载MISFET的源极区域 沿列方向布置的存储单元通过导体层电连接到n型阱区，并且每个导体层独立于沿列方向排列的存储单元而形成。 更具体地，n型阱区域被馈送有第一固定电位，并且每个p沟道型负载MISFET的源极区域通过独立形成的导体层馈送第一固定电位。

    Semiconductor memory device
    8.
    再颁专利
    Semiconductor memory device 有权

    公开(公告)号：USRE38545E1

    公开(公告)日：2004-07-06

    申请号：US09636642

    申请日：2000-08-08

    申请人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    发明人： Toshiro Hiramoto ,  Nobuo Tamba ,  Motoki Kasai

    IPC分类号： H01L2976

    CPC分类号： G11C11/412 ,  H01L27/1104

    摘要： A semiconductor memory device having a plurality of memory cells each comprising two CMOS inverters cross-coupled to each other and arranged at intersections between a plurality of word lines extending in a column direction and a plurality of complementary data line pairs extending in a row direction; wherein p-channel type load MISFETs of the memory cells arranged in the column direction are formed on the main surface of an n-type well region in the direction in which the word lines extend, the source regions of the p-channel type load MISFETs of the memory cells arranged in the column direction are electrically connected to the n-type well region through conductor layers, and each of the conductor layer is formed independently of the memory cells arranged in the column direction. More specifically, the n-type well regions are fed with a first fixed potential, and the source region of each of the p-channel type load MISFETs is fed with the first fixed potential through the conductor layers which are formed independently.

    MOS transistor with a controlled threshold voltage
    10.
    发明授权
    MOS transistor with a controlled threshold voltage 失效
    具有受控阈值电压的MOS晶体管

    公开(公告)号：US06989569B1

    公开(公告)日：2006-01-24

    申请号：US09389321

    申请日：1999-09-03

    申请人： Toshiro Hiramoto ,  Makoto Takamiya

    发明人： Toshiro Hiramoto ,  Makoto Takamiya

    IPC分类号： H01L29/78

    CPC分类号： H01L29/78609 ,  H01L29/783 ,  H01L29/78648

    摘要： A MOS transistor with a controlled threshold voltage includes a SOI which includes a substrate composed of a semi-conducting material, a single crystal layer composed of a semi-conducting material and an insulating layer interposed between the substrate and the single crystal layer. The single crystal layer is formed therein with a source region, a drain region and a surrounded region surrounded by the source region and the drain region. The surrounded region includes a depletion layer having a composition surface which is in contact with the insulating layer. The MOS transistor comprises an EIB-MOS transistor of which the substrate is adapted to be applied with a voltage of a first polarity for inducing charges of a second polarity over the composition surface of the surrounded region.

    摘要翻译： 具有受控阈值电压的MOS晶体管包括SOI，其包括由半导体材料构成的衬底，由半导体材料构成的单晶层和插入在衬底和单晶层之间的绝缘层。 单晶层在其中形成有源极区域，漏极区域和由源极区域和漏极区域包围的被包围的区域。 被包围的区域包括具有与绝缘层接触的组成表面的耗尽层。 MOS晶体管包括EIB-MOS晶体管，其基板适于施加第一极性的电压，用于在所包围的区域的组成表面上诱导第二极性的电荷。