公开(公告)号：US08952315B2

公开(公告)日：2015-02-10

申请号：US12574494

申请日：2009-10-06

Applicant: Kazunobu Ohta ,  Tomoyuki Hirano

Inventor： Kazunobu Ohta ,  Tomoyuki Hirano

IPC: H01L27/00 ,  H01L31/00 ,  H01L31/113 ,  H01L27/146 ,  H01L29/66

CPC classification number: H01L27/14614 ,  H01L27/14634 ,  H01L27/14689 ,  H01L29/66666

Abstract: A solid-state imaging device includes: a pixel part having a photoelectric conversion part photoelectrically converting incident light to obtain signal charge; and a peripheral circuit part formed on a periphery of the pixel part on a semiconductor substrate. The pixel part having a vertical transistor that reads out the signal charge from the photoelectric conversion part and a planar transistor that processes the signal charge read out by the vertical transistor. The vertical transistor has a groove part formed on the semiconductor substrate; a gate insulator film formed on an inner surface of the groove part; a conducting layer formed on a surface of the gate insulator film on the semiconductor substrate within and around the groove part; a filling layer filling an interior of the groove part via the gate insulator film and the conducting layer; and an electrode layer connected to the conducting layer on the filling layer.

Abstract translation: 一种固态成像装置，包括：像素部，具有光电转换部，对入射光进行光电转换，得到信号电荷; 以及形成在半导体衬底上的像素部分的周围的外围电路部分。 像素部分具有从光电转换部读出信号电荷的垂直晶体管和处理由垂直晶体管读出的信号电荷的平面晶体管。 垂直晶体管具有形成在半导体衬底上的沟槽部分; 形成在所述槽部的内表面上的栅极绝缘膜; 导电层，形成在所述半导体衬底的所述栅极绝缘膜的表面上，并且在所述沟槽部内和周围; 填充层，其经由所述栅极绝缘膜和所述导电层填充所述槽部的内部; 以及与填充层上的导电层连接的电极层。

公开(公告)号：US06906393B2

公开(公告)日：2005-06-14

申请号：US10620379

申请日：2003-07-17

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/14 ,  H01L29/82 ,  H01L29/84

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US07960281B2

公开(公告)日：2011-06-14

申请号：US12323507

申请日：2008-11-26

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/44

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US06872642B2

公开(公告)日：2005-03-29

申请号：US10442226

申请日：2003-05-21

Applicant: Hidekazu Oda ,  Hirokazu Sayama ,  Kazunobu Ohta ,  Kouhei Sugihara

Inventor： Hidekazu Oda ,  Hirokazu Sayama ,  Kazunobu Ohta ,  Kouhei Sugihara

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L21/425

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions (16, 36) from their upper surfaces. In the source/drain regions (16, 36), a region shallower than a region where the suppression impurity is distributed (50) is made into silicide, so that a silicide film (51) is formed in the source/drain regions (16, 36). Thus, by making the region shallower than the region (50) into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions (16, 36) and a well region.

Abstract translation: 提供一种制造半导体器件的方法，其可以通过制造硅化物来抑制泄漏电流的增加。 抑制硅化物形成反应（抑制杂质）如锗的杂质从其上表面引入源/漏区（16,36）。 在源极/漏极区域（16,36）中，将比抑制杂质分布区域浅的区域（50）制成硅化物，使得在源极/漏极区域（16）中形成硅化物膜（51） ，36）。 因此，通过使区域（50）的区域比硅化物更浅，可以抑制硅化物形成反应延伸到要制成硅化物的区域的下侧。 这使得能够减少源极/漏极区域（16,36）与阱区域之间的结漏电。

公开(公告)号：US20110207312A1

公开(公告)日：2011-08-25

申请号：US13103558

申请日：2011-05-09

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/283

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅极（14）作为掩模，注入具有相对较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US20090095992A1

公开(公告)日：2009-04-16

申请号：US11962431

申请日：2007-12-21

Applicant: Tomoya SANUKI ,  Kazunobu Ohta

Inventor： Tomoya SANUKI ,  Kazunobu Ohta

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L29/7834 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: Element isolation regions are formed in a semiconductor substrate of a first conductivity type. A gate insulator is formed on the semiconductor substrate between the element isolation regions. A gate electrode is formed on the gate insulator. Sidewall insulating films are formed on side surfaces of the gate electrode. Trenches are formed on the semiconductor substrate between the element isolation regions and the gate electrode. A first epitaxial semiconductor layer of a second conductivity type is formed by the epitaxial growth method in each of the trenches. The first epitaxial semiconductor layer has a facet. A silicide film is formed on the first epitaxial semiconductor layer. A semiconductor region of the second conductivity type is formed in the semiconductor substrate under the first epitaxial semiconductor layer.

Abstract translation: 在第一导电类型的半导体衬底中形成元件隔离区。 在半导体衬底上在元件隔离区之间形成栅极绝缘体。 栅电极形成在栅极绝缘体上。 侧壁绝缘膜形成在栅电极的侧表面上。 在元件隔离区域和栅电极之间的半导体衬底上形成沟槽。 通过外延生长法在每个沟槽中形成第二导电类型的第一外延半导体层。 第一外延半导体层具有小面。 在第一外延半导体层上形成硅化物膜。 在第一外延半导体层下面的半导体衬底中形成第二导电类型的半导体区域。

公开(公告)号：US07470618B2

公开(公告)日：2008-12-30

申请号：US11671216

申请日：2007-02-05

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/44

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US07183204B2

公开(公告)日：2007-02-27

申请号：US11127093

申请日：2005-05-12

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/44

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成NMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成NMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了NMOS晶体管的载流子迁移率。

公开(公告)号：US08372747B2

公开(公告)日：2013-02-12

申请号：US13103558

申请日：2011-05-09

Applicant: Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/44

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US20070128816A1

公开(公告)日：2007-06-07

申请号：US11671216

申请日：2007-02-05

Applicant: Hirokazu SAYAMA ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

Inventor： Hirokazu SAYAMA ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/336

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅电极（14）作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。