公开(公告)号：US20070034940A1

公开(公告)日：2007-02-15

申请号：US11501917

申请日：2006-08-10

申请人： Tomoya Sanuki

发明人： Tomoya Sanuki

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/78 ,  H01L29/7843

摘要： A semiconductor device comprises a gate electrode provided on a gate insulating film, a side wall insulating film provided on a side wall of the gate electrode through a protection insulating film, a barrier SiN film provided to cover the gate electrode and the side wall insulating film, an inter-level insulating film provided to cover the barrier SiN film, and an SOG-series high-stress material being used as part of the inter-level insulating film.

摘要翻译： 半导体器件包括设置在栅极绝缘膜上的栅电极，通过保护绝缘膜设置在栅电极的侧壁上的侧壁绝缘膜，设置成覆盖栅电极和侧壁绝缘膜的阻挡SiN膜 设置为覆盖阻挡SiN膜的层间绝缘膜，以及用作层间绝缘膜的一部分的SOG系高应力材料。

公开(公告)号：US07019380B2

公开(公告)日：2006-03-28

申请号：US10804206

申请日：2004-03-19

申请人： Tomoya Sanuki

发明人： Tomoya Sanuki

IPC分类号： H01L29/00 ,  H01L27/01

CPC分类号： H01L29/78696 ,  H01L27/1203 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/78687

摘要： A semiconductor device includes a semiconductor substrate having an element region, and an element isolation region formed around the element region, the element isolation region being formed of an insulation material having a higher thermal expansion coefficient than the element region.

摘要翻译： 半导体器件包括具有元件区域的半导体衬底和形成在元件区域周围的元件隔离区域，元件隔离区域由具有比元件区域更高的热膨胀系数的绝缘材料形成。

公开(公告)号：US06667503B2

公开(公告)日：2003-12-23

申请号：US10097382

申请日：2002-03-15

申请人： Hidetoshi Koike ,  Tomoya Sanuki

发明人： Hidetoshi Koike ,  Tomoya Sanuki

IPC分类号： H01L2708

CPC分类号： H01L27/10867 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181 ,  H01L29/945

摘要： Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

摘要翻译： 由于沟槽电容器电极的至少一部分由金属形成，所以电极的电薄膜电阻可以降低，并且可以缩短由CR延迟延长的信号传播时间。 这可以减少读/写时间。 掩埋栅电极的形成可以实现DRAM和DRAM /逻辑嵌入式设备中所需的单元面积的减小。 这可以增加栅极长度并减少短沟道效应。 由于绝缘保护膜沉积在栅电极上，所以可以自对准地形成位线接触。

公开(公告)号：US06989560B2

公开(公告)日：2006-01-24

申请号：US10676123

申请日：2003-10-02

申请人： Hidetoshi Koike ,  Tomoya Sanuki

发明人： Hidetoshi Koike ,  Tomoya Sanuki

IPC分类号： H01L27/108 ,  H01L21/8239 ,  G11C11/24

CPC分类号： H01L27/10867 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10864 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/66181 ,  H01L29/945

摘要： Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

公开(公告)号：US20110233685A1

公开(公告)日：2011-09-29

申请号：US13051533

申请日：2011-03-18

申请人： Takayuki Ito ,  Kenichi Yoshino ,  Tomoya Sanuki ,  Hiroshi Ohno

发明人： Takayuki Ito ,  Kenichi Yoshino ,  Tomoya Sanuki ,  Hiroshi Ohno

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L21/268 ,  H01L21/02694 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/28123 ,  H01L21/823412 ,  H01L27/0207 ,  H01L27/088

摘要： According to embodiments, there is provided a semiconductor device, including: a first area including plural transistors formed therein; and a second area including plural dummy transistors formed therein, the second area surrounding the first area, wherein a pitch of the dummy transistors is equal to or less than a central wavelength of a light used to form the transistors.

摘要翻译： 根据实施例，提供了一种半导体器件，包括：形成在其中的多个晶体管的第一区域; 以及包括形成在其中的多个虚设晶体管的第二区域，围绕第一区域的第二区域，其中虚设晶体管的间距等于或小于用于形成晶体管的光的中心波长。

公开(公告)号：US07737466B1

公开(公告)日：2010-06-15

申请号：US11889420

申请日：2007-08-13

申请人： Kaoru Hiyama ,  Tomoya Sanuki ,  Osamu Fujii

发明人： Kaoru Hiyama ,  Tomoya Sanuki ,  Osamu Fujii

IPC分类号： H01L29/06 ,  H01L35/26

CPC分类号： H01L21/823807 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/10894 ,  H01L29/92

摘要： A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

摘要翻译： 半导体器件包括具有与第一区域相邻的第一区域和第二区域的衬底，设置在第一区域中的衬底上的第一硅层，设置在第二区域中的衬底上的松弛层， 晶格常数大于第一硅层的晶格常数，以及设置在松弛层上并具有与弛豫层的晶格常数基本相等的晶格常数的应变Si层。

公开(公告)号：US20090095992A1

公开(公告)日：2009-04-16

申请号：US11962431

申请日：2007-12-21

申请人： Tomoya SANUKI ,  Kazunobu Ohta

发明人： Tomoya SANUKI ,  Kazunobu Ohta

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L21/28518 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： Element isolation regions are formed in a semiconductor substrate of a first conductivity type. A gate insulator is formed on the semiconductor substrate between the element isolation regions. A gate electrode is formed on the gate insulator. Sidewall insulating films are formed on side surfaces of the gate electrode. Trenches are formed on the semiconductor substrate between the element isolation regions and the gate electrode. A first epitaxial semiconductor layer of a second conductivity type is formed by the epitaxial growth method in each of the trenches. The first epitaxial semiconductor layer has a facet. A silicide film is formed on the first epitaxial semiconductor layer. A semiconductor region of the second conductivity type is formed in the semiconductor substrate under the first epitaxial semiconductor layer.

摘要翻译： 在第一导电类型的半导体衬底中形成元件隔离区。 在半导体衬底上在元件隔离区之间形成栅极绝缘体。 栅电极形成在栅极绝缘体上。 侧壁绝缘膜形成在栅电极的侧表面上。 在元件隔离区域和栅电极之间的半导体衬底上形成沟槽。 通过外延生长法在每个沟槽中形成第二导电类型的第一外延半导体层。 第一外延半导体层具有小面。 在第一外延半导体层上形成硅化物膜。 在第一外延半导体层下面的半导体衬底中形成第二导电类型的半导体区域。

公开(公告)号：US20090057777A1

公开(公告)日：2009-03-05

申请号：US12263830

申请日：2008-11-03

申请人： Osamu FUJII ,  Tomoya SANUKI

发明人： Osamu FUJII ,  Tomoya SANUKI

IPC分类号： H01L27/092

CPC分类号： H01L29/7846 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7842

摘要： A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the isolating insulation film is broken.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的多个晶体管和用于将多个晶体管彼此隔离的隔离区域，隔离区域由隔离绝缘膜组成，其中至少具有晶体结构 隔离绝缘膜的一部分断裂。

公开(公告)号：US20070290208A1

公开(公告)日：2007-12-20

申请号：US11889451

申请日：2007-08-13

申请人： Kaoru Hiyama ,  Tomoya Sanuki ,  Osamu Fujii

发明人： Kaoru Hiyama ,  Tomoya Sanuki ,  Osamu Fujii

IPC分类号： H01L29/10

CPC分类号： H01L21/823807 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/10894 ,  H01L29/92

摘要： A semiconductor device includes a substrate having a first area and a second area adjacent to the first area, a first silicon layer provided on the substrate in the first area, a relaxed layer which is provided on the substrate in the second area and which has a lattice constant greater than a lattice constant of the first silicon layer, and a strained-Si layer which is provided on the relaxed layer and which has a lattice constant substantially equivalent to the lattice constant of the relaxed layer.

摘要翻译： 半导体器件包括具有与第一区域相邻的第一区域和第二区域的衬底，设置在第一区域中的衬底上的第一硅层，设置在第二区域中的衬底上的松弛层， 晶格常数大于第一硅层的晶格常数，以及设置在松弛层上并具有与弛豫层的晶格常数基本相等的晶格常数的应变Si层。

公开(公告)号：US07605442B2

公开(公告)日：2009-10-20

申请号：US12263830

申请日：2008-11-03

申请人： Osamu Fujii ,  Tomoya Sanuki

发明人： Osamu Fujii ,  Tomoya Sanuki

IPC分类号： H01L21/762

CPC分类号： H01L29/7846 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/7842

摘要： A semiconductor device comprises a semiconductor substrate, a plurality of transistors provided in the semiconductor substrate, and an isolation region for isolating the plurality of transistors to one another, the isolation region being comprised of an isolating insulation film, wherein a crystal structure of at least a part of the isolating insulation film is broken.

摘要翻译： 半导体器件包括半导体衬底，设置在半导体衬底中的多个晶体管和用于将多个晶体管彼此隔离的隔离区域，隔离区域由隔离绝缘膜组成，其中至少具有晶体结构 隔离绝缘膜的一部分被破坏。