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    SEMICONDUCTOR INTEGRATED CIRCUIT
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20100295585A1

    公开(公告)日：2010-11-25

    申请号：US12851597

    申请日：2010-08-06

    申请人： KAZUO YAMAKIDO ,  Takashi Nakamura

    发明人： KAZUO YAMAKIDO ,  Takashi Nakamura

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

    摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

    摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    半导体集成电路

    公开(公告)号：US20090195277A1

    公开(公告)日：2009-08-06

    申请号：US12365743

    申请日：2009-02-04

    申请人： Kazuo YAMAKIDO ,  Takashi Nakamura

    发明人： Kazuo YAMAKIDO ,  Takashi Nakamura

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

    摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

    摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括控制数据存储电路，用于预先存储用于锁定操作的初始设置数据集。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

    Semiconductor integrated circuit
    3.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07888981B2

    公开(公告)日：2011-02-15

    申请号：US12851597

    申请日：2010-08-06

    申请人： Kazuo Yamakido ,  Takashi Nakamura

    发明人： Kazuo Yamakido ,  Takashi Nakamura

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

    摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

    摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07786776B2

    公开(公告)日：2010-08-31

    申请号：US12365743

    申请日：2009-02-04

    申请人： Kazuo Yamakido ,  Takashi Nakamura

    发明人： Kazuo Yamakido ,  Takashi Nakamura

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

    摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

    摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20110115569A1

    公开(公告)日：2011-05-19

    申请号：US13010224

    申请日：2011-01-20

    申请人： KAZUO YAMAKIDO ,  Takashi Nakamura

    发明人： KAZUO YAMAKIDO ,  Takashi Nakamura

    IPC分类号： H03L7/06 ,  H03L7/00

    CPC分类号： H03L7/0995 ,  H03L7/085 ,  H03L7/093 ,  H03L2207/50

    摘要： The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.

    摘要翻译： 半导体集成电路包括具有可操作以产生时钟信号的数字控制信号产生部分和数字控制部分的时钟产生部分。 时钟产生部分还包括相位频率比较器和控制寄存器。 比较器被提供有参考信号CLKin和反馈信号。 控制寄存器提供比较器的输出信号，并存储两个或更多位的数字控制信息。 时钟产生部分还包括用于预先存储用于锁定操作的初始设置数据集合的控制数据存储电路。 响应于操作选择信息，初始设定数据被存储在来自控制数据存储电路的控制寄存器的高位。 因此，可以减少将控制信息存储在用于数字控制时钟信号产生部分的寄存器中的步骤数。

    SEPP-Based deflection control circuit
    6.
    发明授权
    SEPP-Based deflection control circuit 失效
    基于SEPP的偏转控制电路

    公开(公告)号：US4409613A

    公开(公告)日：1983-10-11

    申请号：US354307

    申请日：1982-03-03

    申请人： Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji ,  Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji

    发明人： Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji ,  Takashi Nakamura ,  Yoshihiro Morioka ,  Kazunori Yamaji

    IPC分类号： H04N3/16 ,  H04N3/22 ,  H04N9/09 ,  H04N9/093

    CPC分类号： H04N9/09

    摘要： Deflection control apparatus for registering the electron beam, rasters of electrostatic-deflection pick-up tubes of a three-tube color television camera includes a compensating voltage generator with inputs connected to receive horizontal and vertical sawtooth deflection signals provided from a deflection signal generator, and outputs providing compensating voltages to adjust for size, skew, and rotation. A combining circuit is provided to add the deflecting signals to the respective compensating voltages to generate adjusted compensating voltages for application to respective electrostatic deflection plates of certain ones of the tubes. For each adjusted deflecting signal, the combining circuit includes a transistor circuit having an input electrode coupled to receive the associated compensating voltage and an output electrode connected through a load resistor to an output of the deflecting signal generator. A pair of SEPP-arranged transistors are provided with their bases connected to the output electrode of the transistor circuit and with their emitters coupled together, through like-value emitter resistors, to a respective deflection plate of one of the tubes. The SEPP-configured transistors permit a high impedance to be presented to the deflection signal generator to minimize the power consumption thereof, and a low resistance to be presented to the deflection plates, to keep the latter from undesirably integrating the deflection sawtooth voltages.

    摘要翻译： 用于对电子束进行配准的偏转控制装置，三管彩色电视摄像机的静电偏转拾取管的光栅包括：补偿电压发生器，具有连接的输入端，用于接收从偏转信号发生器提供的水平和垂直锯齿波偏转信号;以及 输出提供补偿电压以调整大小，偏斜和旋转。 提供组合电路以将偏转信号添加到相应的补偿电压以产生用于施加到某些管的各个静电偏转板的调整的补偿电压。 对于每个经调整的偏转信号，组合电路包括晶体管电路，其具有耦合以接收相关联的补偿电压的输入电极和通过负载电阻器连接到偏转信号发生器的输出的输出电极。 一对SEPP布置的晶体管被​​设置有它们的基极连接到晶体管电路的输出电极，并且它们的发射极通过同值发射极电阻耦合到一个管的相应的偏转板上。 SEPP配置的晶体管允许将高阻抗呈现给偏转信号发生器以最小化其功率消耗，以及将低电阻提供给偏转板，以防止偏转锯齿波电压的不期望的积分。

    ELECTRONIC DEVICE
    9.
    发明申请
    ELECTRONIC DEVICE 审中-公开
    电子设备

    公开(公告)号：US20130223025A1

    公开(公告)日：2013-08-29

    申请号：US13588100

    申请日：2012-08-17

    申请人： Tadaomi Fujieda ,  Takashi Nakamura

    发明人： Tadaomi Fujieda ,  Takashi Nakamura

    IPC分类号： H05K7/02

    CPC分类号： H05K7/02 ,  G06F1/1656

    摘要： Provided is an electronic device including a housing, at least a part of which has conductive properties; a substrate on which a heating element is mounted and which has a ground pattern; and a spacer which is located between the housing and the ground pattern and which includes a main body portion having heat insulating properties and a conductive portion which is in contact with the ground pattern and the housing and which conducts current between the ground pattern and the housing.

    摘要翻译： 提供一种电子设备，其包括壳体，其至少一部分具有导电性能; 其上安装有加热元件并具有接地图案的基板; 以及间隔件，其位于壳体和接地图案之间，并且包括具有绝热性能的主体部分和与接地图案和壳体接触的导电部分并且在接地图案和壳体之间传导电流的间隔件 。