公开(公告)号：US5949486A

公开(公告)日：1999-09-07

申请号：US795217

申请日：1997-02-05

申请人： Kazuya Ishihara ,  Shinichi Uramoto ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami ,  Shinichi Masuda

发明人： Kazuya Ishihara ,  Shinichi Uramoto ,  Tetsuya Matsumura ,  Satoshi Kumaki ,  Atsuo Hanami ,  Shinichi Masuda

IPC分类号： H04N19/50 ,  H03M7/30 ,  H03M7/36 ,  H04N5/14 ,  H04N19/423 ,  H04N19/436 ,  H04N19/51 ,  H04N7/12

CPC分类号： H04N19/433 ,  H04N19/51 ,  H04N5/145

摘要： Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

摘要翻译： 与模板块和搜索窗口块的像素相对应地布置的每个元素处理器分别包括彼此并行提供的用于存储搜索窗口块像素数据的A寄存器和B寄存器，以及用于存储模板块的T寄存器 像素数据。 通过A和B寄存器中的第一个和存储在T寄存器中的像素数据执行运动矢量评估值计算，而操作数据从A和B中的第一个传送到A和B寄存器中的第二个， B与计算操作并行登记，用于存储下一个搜索窗口的头部搜索窗口块像素数据。 以良好的编码效率高速检测运动矢量。

公开(公告)号：US5701267A

公开(公告)日：1997-12-23

申请号：US578892

申请日：1995-12-27

申请人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

发明人： Shinichi Masuda ,  Satoshi Kumaki ,  Yoshinori Matsuura

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/22 ,  G11C29/56 ,  G11C13/00

CPC分类号： G11C7/00 ,  G11C29/003

摘要： It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

摘要翻译： 本发明的目的是实现诸如FIFO存储器等的宏小区中的输入数据的旁路，以便于关于其他宏小区的测试和评估。 旁路路径（6）设置在FIFO存储器（1）中的输入端口（DI）和输出端口（DO）之间，并且数据旁路选择器（8）还被设置用于选择旁路路径（6）和 读位线（RBL）的读出放大器（7）。 然后，在测试模式中，将第一选择器控制信号（S）设置为L电平，将相反相位的第二选择器控制信号（+ E，ovs S + EE）设置为H电平。 因此，在测试模式中，从输入端口（DI）输入的数据通过旁路路径（6）从输出端口（DO）输出，而不经由存储单元（MC1-MCX）输出。

公开(公告)号：US5732249A

公开(公告)日：1998-03-24

申请号：US578432

申请日：1995-12-26

申请人： Shinichi Masuda ,  Kazuya Ishihara

发明人： Shinichi Masuda ,  Kazuya Ishihara

IPC分类号： G06F1/10 ,  H03K5/15 ,  H03K19/0175 ,  G06F1/04

CPC分类号： G06F1/10

摘要： To improve the clock delay time and skew. A first resistance body (R1) and a second resistance body (R2) are provided at a terminal end node (N5) of a clock trunk line (1) composed of a doped polysilicon film or the like. Their elements (R1), (R2) are composed of the same film as the clock trunk line (1). Their resistance ratio is set so that the clamp level may be an inverted threshold of first and second local drivers (D2, D3), and the resistance values of both resistance bodies (R1, R2), and the value of interconnection resistance (R) of the clock trunk line (1) are set so that an amplitude of a clock signal at each of the nodes (N3, N4, N5) may be a potential corresponding to 1/2 of its peak-to-peak voltage at the same time. The amplitude of the clock signal from a start end node (N3) to a terminal end node (N5) decreases, and the delay time from an output of a clock driver (D1) to outputs of the local drivers (D2, D3) shaped in waveform is much shorter, and hence the clock skew of the outputs hardly occurs.

摘要翻译： 提高时钟延迟时间和偏移。 在由掺杂多晶硅膜等构成的时钟主干线（1）的终端节点（N5）上设置有第一电阻体（R1）和第二电阻体（R2）。 它们的元件（R1），（R2）由与时钟主干线（1）相同的膜组成。 设置它们的电阻比，使得钳位电平可以是第一和第二局部驱动器（D2，D3）的反相阈值，并且两个电阻体（R1，R2）的电阻值和互连电阻值（R） 时钟中继线（1）的时钟信号的幅度被设置为使得每个节点（N3，N4，N5）处的时钟信号的幅度可以是对应于+ E的电位，其峰值的频率为1/2 + EE -peak电压同时。 从起始端节点（N3）到终端节点（N5）的时钟信号的幅度减小，并且从时钟驱动器（D1）的输出到本地驱动器（D2，D3）的输出的延迟时间成形 波形较短，因此几乎不发生输出的时钟偏移。

公开(公告)号：US5410513A

公开(公告)日：1995-04-25

申请号：US958051

申请日：1992-10-08

申请人： Shinichi Masuda ,  Masatoshi Kimura ,  Tetsuya Matsumura

发明人： Shinichi Masuda ,  Masatoshi Kimura ,  Tetsuya Matsumura

IPC分类号： G11C8/04 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C8/04

摘要： A counter counts clock signals. When a count thereof coincides with the number of rows or columns in a memory cell array, a row or column count coincidence signal is generated and applied to a shift input of a row or column address pointer formed of shift registers. The row or column address pointer is responsive to the clock signals to sequentially shift the count coincidence signal applied to the shift input, so that row or column selecting lines in the memory cell array are sequentially set in the selected state. Since the outputs at final stages in the row and column address pointers are not fed back to the inputs at the first stage thereof, signal delay in a feed back path is not caused, and thus operations for selecting rows and columns are performed at high speed. Also, respective shift register stages in the row and column address pointers have the same construction, and thus regularity thereof is maintained.

公开(公告)号：US5448530A

公开(公告)日：1995-09-05

申请号：US305985

申请日：1994-09-19

申请人： Shinichi Masuda ,  Masatoshi Kimura ,  Tetsuya Matsumura

发明人： Shinichi Masuda ,  Masatoshi Kimura ,  Tetsuya Matsumura

IPC分类号： G11C8/04 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C8/04

摘要： A counter counts clock signals. When a count thereof coincides with the number of rows or columns in a memory cell array, a row or column count coincidence signal is generated and applied to a shift input of a row or column address pointer formed of shift registers. The row or column address pointer is responsive to the clock signals to sequentially shift the count coincidence signal applied to the shift input, so that row or column selecting lines in the memory cell array are sequentially set in the selected state. Since the outputs at final stages in the row and column address pointers are not fed back to the inputs at the first stage thereof, signal delay in a feed back path is not caused, and thus operations for selecting rows and columns are performed at high speed. Also, respective shift register stages in the row and column address pointers have the same construction, and thus regularity thereof is maintained.

摘要翻译： 计数器计数时钟信号。 当其计数与存储单元阵列中的行或列的数量一致时，生成行或列计数符合信号并将其应用于由移位寄存器形成的行或列​​地址指针的移位输入。 行或列地址指针响应于时钟信号以顺序地移动施加到移位输入的计数符合信号，使得存储单元阵列中的行或列选择线被顺序地设置为选择状态。 由于在行和列地址指针的最后阶段的输出在其第一阶段不被反馈到输入，所以不会引起反馈路径中的信号延迟，因此用于选择行和列的操作以高速执行 。 此外，行和列地址指针中的各个移位寄存器级具有相同的结构，因此保持其规律性。

公开(公告)号：US20100254688A1

公开(公告)日：2010-10-07

申请号：US12752743

申请日：2010-04-01

申请人： Shinichi Masuda

发明人： Shinichi Masuda

IPC分类号： G03B17/00

CPC分类号： G03B17/00

摘要： Provided is an image shake correction apparatus including: an image taking optical system for taking an image of a subject; an angular velocity detection unit for detecting an angular velocity applied to the apparatus and outputting a first signal; an acceleration detection unit for detecting an acceleration applied to the apparatus and outputting a second signal; an axial rotation angular velocity calculation unit for calculating an axial rotation angular velocity component about a principal point of the image taking optical system based on the first signal; a revolution angular velocity calculation unit for calculating a revolution angular velocity component about the subject based on the second signal and a result of the calculating by the axial rotation angular velocity calculation unit; and a control unit for performing image shake correction control based on a difference between the axial rotation angular velocity component and the revolution angular velocity component.

摘要翻译： 提供一种图像抖动校正装置，包括：拍摄对象的图像拍摄光学系统; 角速度检测单元，用于检测施加到装置的角速度并输出第一信号; 加速度检测单元，用于检测施加到所述装置的加速度并输出第二信号; 轴向旋转角速度计算单元，用于基于第一信号计算围绕摄像光学系统的主点的轴向旋转角速度分量; 旋转角速度计算单元，用于基于所述第二信号计算所述被摄体的旋转角速度分量，以及所述轴向旋转角速度计算单元计算的结果; 以及控制单元，用于基于轴向旋转角速度分量和旋转角速度分量之间的差进行图像抖动校正控制。

公开(公告)号：US07553094B2

公开(公告)日：2009-06-30

申请号：US11156108

申请日：2005-06-17

申请人： Shinichi Masuda ,  Eriko Namazue

发明人： Shinichi Masuda ,  Eriko Namazue

IPC分类号： G03B9/02 ,  G03B9/10 ,  H04N5/238

CPC分类号： H04N5/2254 ,  G03B9/06 ,  H04N5/238

摘要： At least one exemplary embodiment is directed to a light quantity adjusting apparatus that can include a first blade member configured to be driven by a drive source, such as a motor, and a second blade member whose movement is configured to be related to the movement of the first blade member.

摘要翻译： 至少一个示例性实施例涉及一种光量调节装置，该光量调节装置可以包括构造成由诸如马达的驱动源驱动的第一叶片构件，以及第二叶片构件，其移动被配置为与 第一刀片构件。

公开(公告)号：US07374353B2

公开(公告)日：2008-05-20

申请号：US11245692

申请日：2005-10-07

申请人： Shinichi Masuda

发明人： Shinichi Masuda

IPC分类号： G03B9/00 ,  G03B9/08

CPC分类号： G03B9/06 ,  G03B9/10 ,  G03B9/24

摘要： There is provided a light control apparatus that maintains the overall apparatus size small, increases the number of stop stages, and is suitable for both the shutter and stop actions. A light control apparatus includes a first actuator, a second actuator, a first light shielding member driven by the first actuator, and a second light shielding member driven by the second actuator, wherein in a stop adjusting action, the first and second actuators drive the first and second light shielding members and adjust an aperture formed by the first and second light shielding members, and wherein in a shutter action, the second actuator drives the second light-shielding member for a light shielding action.

摘要翻译： 提供了一种将整体装置尺寸维持在较小的光控制装置，增加了停止阶段的数量，并且适用于快门和停止动作两者。 光控制装置包括第一致动器，第二致动器，由第一致动器驱动的第一遮光部件和由第二致动器驱动的第二遮光部件，其中，在停止调整动作中，第一致动器和第二致动器驱动 第一和第二遮光构件，并且调节由第一和第二遮光构件形成的孔，并且其中在快门动作中，第二致动器驱动第二遮光构件以进行遮光动作。

公开(公告)号：US07230219B2

公开(公告)日：2007-06-12

申请号：US10558423

申请日：2004-05-25

申请人： Shinobu Miyazaki ,  Masaki Nakaishi ,  Shinichi Masuda

发明人： Shinobu Miyazaki ,  Masaki Nakaishi ,  Shinichi Masuda

IPC分类号： H05B6/68 ,  H02M3/335

CPC分类号： H02M1/4208 ,  Y02B70/126

摘要： An oscillation control signal generated by an inverter power source control circuit (12) includes a reference voltage setting signal for approximating the current waveform of the AC output form the AC power source (1) to a sinusoidal wave by making both sides of the waveform generate current according to the fluctuation of the PWM control signal, and a waveform shaping signal consisting of a peak adjustment signal of a sinusoidal waveform for approximating the waveform peak portion of the current waveform to a sinusoidal wave by subtraction. Accordingly, even if the PWM control signal fluctuates, it is possible to automatically improve the power factor of the power source circuit to a value higher than a predetermined value by approximating the current waveform of the AC output from the AC power source to the sinusoidal wave, thereby improving the efficiency of the power source.

摘要翻译： 由逆变器电源控制电路（12）产生的振荡控制信号包括参考电压设定信号，用于通过使波形的两侧生成来将从AC电源（1）输出的AC电流的电流波形近似为正弦波 根据PWM控制信号的波动的电流以及由用于通过减法将电流波形的波形峰值部分近似为正弦波的正弦波形的峰值调整信号组成的波形整形信号。 因此，即使PWM控制信号波动，也可以通过将从AC电源输出的AC的电流波形近似为正弦波，从而将电源电路的功率因数自动地提高到高于预定值的值 ，从而提高电源的效率。

公开(公告)号：US20060186102A1

公开(公告)日：2006-08-24

申请号：US11349112

申请日：2006-02-08

申请人： Isao Inagaki ,  Satoru Kowaki ,  Shinichi Masuda ,  Hideyuki Komatsu

发明人： Isao Inagaki ,  Satoru Kowaki ,  Shinichi Masuda ,  Hideyuki Komatsu

IPC分类号： B23K9/10

CPC分类号： H01H9/04 ,  H01H9/063 ,  H01H9/52

摘要： To provide a trigger switch having a simple structure that is capable of reducing bouncing when the contacts are switched ON/OFF, the trigger switch includes a switch mechanism integrated in a single assembly a power control unit that turns a plurality of switches provided on the switch mechanism ON/OFF depending on a degree of retraction of the control unit by moving a pressing member over a top of a seesaw-shaped switching bar, a motor brake and control element short-circuit unit that drives a movable armature having two short-circuit contacts and is sandwiched and held between two springs, and a speed control unit that slides a plurality of moving contacts disposed in parallel over sliding contacts disposed on a sliding circuit substrate so as to control both the supply of power and a control element, and thus control the rotation speed of a motor.