公开(公告)号：US06878579B2

公开(公告)日：2005-04-12

申请号：US10917345

申请日：2004-08-13

申请人： Kazuya Ohuchi ,  Hironobu Fukui

发明人： Kazuya Ohuchi ,  Hironobu Fukui

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L21/335 ,  H01L21/425

CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S438/904 ,  Y10S438/917 ,  Y10S438/933

摘要： An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

公开(公告)号：US06791106B2

公开(公告)日：2004-09-14

申请号：US10420884

申请日：2003-04-23

申请人： Kazuya Ohuchi ,  Hironobu Fukui

发明人： Kazuya Ohuchi ,  Hironobu Fukui

IPC分类号： H01L2906

CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S438/904 ,  Y10S438/917 ,  Y10S438/933

摘要： An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

摘要翻译： 本发明的一个方面包括第一导电型半导体区域; 形成在所述第一导电型半导体区域上的栅电极; 形成在所述第一导电型半导体区域中的所述栅电极的正下方的沟道区域; 以及构成在第一导电型半导体区域的沟道区的相对侧的源/漏区的第二导电型第一扩散层，栅电极由多晶硅锗形成，其中锗浓度从 漏极区域侧到源极区域侧，并且根据栅极电极中的锗浓度，在第一导电型半导体区域中的栅电极正下方的杂质浓度从源极区域侧向漏极区域侧连续增加。

公开(公告)号：US20050012088A1

公开(公告)日：2005-01-20

申请号：US10917345

申请日：2004-08-13

申请人： Kazuya Ohuchi ,  Hironobu Fukui

发明人： Kazuya Ohuchi ,  Hironobu Fukui

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/76 ,  H01L29/94 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/062 ,  H01L31/072 ,  H01L31/109 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66666 ,  H01L29/7827 ,  Y10S438/904 ,  Y10S438/917 ,  Y10S438/933

摘要： An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.

摘要翻译： 本发明的一个方面包括第一导电型半导体区域; 形成在所述第一导电型半导体区域上的栅电极; 形成在所述第一导电型半导体区域中的所述栅电极的正下方的沟道区域; 以及构成在第一导电型半导体区域的沟道区的相对侧的源/漏区的第二导电型第一扩散层，栅电极由多晶硅锗形成，其中锗浓度从 漏极区域侧到源极区域侧，并且根据栅极电极中的锗浓度，在第一导电型半导体区域中的栅电极正下方的杂质浓度从源极区域侧向漏极区域侧连续增加。

公开(公告)号：US07923756B2

公开(公告)日：2011-04-12

申请号：US12131044

申请日：2008-05-31

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L27/088

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

摘要翻译： 具有金属氧化物半导体（MOS）型晶体管结构的半导体器件，其用于例如 静态随机存取存储器（SRAM）型存储器单元包括容易受到软错误的部分。 在具有MOS型晶体管结构的半导体器件中，在易受软错误的部分形成额外的负载电容。

公开(公告)号：US07394119B2

公开(公告)日：2008-07-01

申请号：US10811107

申请日：2004-03-26

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

摘要翻译： 具有金属氧化物半导体（MOS）型晶体管结构的半导体器件，其用于例如 静态随机存取存储器（SRAM）型存储单元包括容易受到软错误的部分。 在具有MOS型晶体管结构的半导体器件中，在易受软错误的部分形成额外的负载电容。

公开(公告)号：US07723231B2

公开(公告)日：2010-05-25

申请号：US11889576

申请日：2007-08-14

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L21/00

CPC分类号： H01L21/28518 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6656

摘要： A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

摘要翻译： 提供了包括对应于扩散层结深度的不同厚度的硅化物层的半导体器件及其制造方法。 根据一个方面，提供一种包括第一半导体元件器件和第二半导体元件器件的半导体器件，其中所述第一半导体元件器件包括第一栅电极，所述第一扩散层设置为夹着所述第一栅电极，并且具有 第一结深度，以及设置在第一扩散层中并具有第一厚度的第一硅化物层，并且第二半导体元件器件包括第二栅电极，第二扩散层设置为夹持第二栅电极，并具有第二结深度 大于第一结深度的第二硅化物层，以及设置在第二扩散层中并具有大于第一厚度的第二厚度的第二硅化物层。

公开(公告)号：US20090289307A1

公开(公告)日：2009-11-26

申请号：US12470947

申请日：2009-05-22

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L27/092

CPC分类号： H01L27/1104 ,  H01L27/0207 ,  H01L27/11

摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be substantially parallel to the N-type element region and including P-type source/drain regions; P-type well contact connections and N-type well contact connections formed on both sides of the N-type and P-type element regions in a longitudinal direction outside the SRAM region on the semiconductor substrate, respectively; an element isolation region for isolating the N-type element region, the P-type element region, the P-type well contact connection and the N-type well contact connection; a P-type well continuously formed under the N-type element region and the P-type well contact connection in the semiconductor substrate, and an N-type well continuously formed under the P-type element region and the N-type well contact connection in the semiconductor substrate.

摘要翻译： 根据一个实施例的半导体器件包括：具有SRAM区域的半导体衬底; 形成在半导体衬底上的SRAM区中并包括N型源/漏区的N型元件区; 形成在半导体衬底上的SRAM区域中以与N型元件区域基本平行并包括P型源极/漏极区域的P型元件区域; P型阱接触连接和N型阱接触连接分别形成在半导体衬底上的SRAM区域外侧的纵向上的N型和P型元件区的两侧; 用于隔离N型元件区域，P型元件区域，P型阱接触连接和N型阱接触连接的元件隔离区域; 在N型元件区域连续形成的P型阱和半导体衬底中的P型阱接触连接，以及在P型元件区域和N型阱接触连接下连续形成的N型阱 在半导体衬底中。

公开(公告)号：US20110156160A1

公开(公告)日：2011-06-30

申请号：US13045445

申请日：2011-03-10

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L27/092

CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

摘要翻译： 具有金属氧化物半导体（MOS）型晶体管结构的半导体器件，其用于例如 静态随机存取存储器（SRAM）型存储器单元包括容易受到软错误的部分。 在具有MOS型晶体管结构的半导体器件中，在易受软错误的部分形成额外的负载电容。

公开(公告)号：US20080044991A1

公开(公告)日：2008-02-21

申请号：US11889576

申请日：2007-08-14

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： H01L21/3205

CPC分类号： H01L21/28518 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6656

摘要： A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

摘要翻译： 提供了包括对应于扩散层结深度的不同厚度的硅化物层的半导体器件及其制造方法。 根据一个方面，提供一种包括第一半导体元件器件和第二半导体元件器件的半导体器件，其中所述第一半导体元件器件包括第一栅电极，所述第一扩散层设置为夹着所述第一栅电极，并且具有 第一结深度，以及设置在第一扩散层中并具有第一厚度的第一硅化物层，并且第二半导体元件器件包括第二栅电极，第二扩散层设置为夹持第二栅电极，并具有第二结深度 大于第一结深度的第二硅化物层，以及设置在第二扩散层中并具有大于第一厚度的第二厚度的第二硅化物层。

公开(公告)号：US20070097728A1

公开(公告)日：2007-05-03

申请号：US11444526

申请日：2006-06-01

申请人： Hironobu Fukui

发明人： Hironobu Fukui

IPC分类号： G11C11/00

CPC分类号： G11C11/4125 ,  G11C5/005

摘要： A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a time when the input data has a second level. In the second data holding unit, a probability of a soft error at a time when the input data has the second level is lower than a probability of a soft error at a time when the input data has the first level. The selection unit selects an output from the first data holding unit when the input data has the first level, and selects an output from the second data holding unit when the input data has the second level.

摘要翻译： 数据保持电路包括第一数据保持单元，第二数据保持单元和选择单元。 在第一数据保持单元中，当输入数据具有第一电平时，软错误的概率低于输入数据具有第二电平时的软错误的概率。 在第二数据保持单元中，当输入数据具有第二电平时，软错误的概率低于输入数据具有第一电平时的软错误的概率。 当输入数据具有第一电平时，选择单元选择来自第一数据保持单元的输出，并且当输入数据具有第二电平时，选择来自第二数据保持单元的输出。