公开(公告)号：US5328864A

公开(公告)日：1994-07-12

申请号：US699024

申请日：1991-05-13

申请人： Keiichi Yoshizumi ,  Satoshi Kudo

发明人： Keiichi Yoshizumi ,  Satoshi Kudo

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28026 ,  H01L21/823842 ,  Y10S148/106

摘要： The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped to form discrete semiconductor regions.

摘要翻译： 本发明涉及半导体器件的制造方法。 在形成有P型的第一半导体区域和形成在第一和第二半导体区域之间并延伸到第一和第二半导体区域中的N型的第二半导体区域和绝缘膜的半导体衬底中，多晶硅层和 在覆盖第一和第二半导体区域的绝缘膜上形成硅化物层。 位于第一半导体区域上的栅电极具有面对并位于位于第二半导体区域上的栅电极的端部的端部。 掩模层形成在第二半导体区上，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。 第一半导体区域掺杂有N型杂质，从而在第一半导体区域中形成第三半导体区域。 从第二半导体区域去除掩模层，并且在第一半导体区域上形成掩模层，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。 第二半导体区域掺杂有P型杂质，从而在第二半导体区域中形成第四半导体区域。 通过提供掩模层落在栅电极的端部之间，栅电极被离散地掺杂以形成分立的半导体区域。

公开(公告)号：US5032537A

公开(公告)日：1991-07-16

申请号：US509445

申请日：1990-04-16

申请人： Keiichi Yoshizumi ,  Satoshi Kudo

发明人： Keiichi Yoshizumi ,  Satoshi Kudo

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/28026 ,  H01L21/823842 ,  Y10S148/106

摘要： The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped with either the N-type impurity or the P-type impurity to form discrete semiconductor regions.

摘要翻译： 本发明涉及半导体器件的制造方法。 在形成有P型的第一半导体区域和形成在第一和第二半导体区域之间并延伸到第一和第二半导体区域中的N型的第二半导体区域和绝缘膜的半导体衬底中，多晶硅层和 在覆盖第一和第二半导体区域的绝缘膜上形成硅化物层。 位于第一半导体区域上的栅电极具有面对并位于位于第二半导体区域上的栅电极的端部的端部。 掩模层形成在第二半导体区上，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。 第一半导体区域掺杂有N型杂质，从而在第一半导体区域中形成第三半导体区域。 从第二半导体区域去除掩模层，并且在第一半导体区域上形成掩模层，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。 第二半导体区域掺杂有P型杂质，从而在第二半导体区域中形成第四半导体区域。 通过提供掩模层落在栅电极的端部之间，栅电极离散地掺杂有N型杂质或P型杂质以形成分立的半导体区域。

公开(公告)号：US07797851B2

公开(公告)日：2010-09-21

申请号：US11919557

申请日：2007-05-08

申请人： Takanori Funabashi ,  Keiichi Yoshizumi

发明人： Takanori Funabashi ,  Keiichi Yoshizumi

IPC分类号： G01B5/016 ,  G01B7/016

CPC分类号： G01B5/012 ,  G01B7/012 ,  G01B11/007

摘要： There are provided a shape measurement device capable of measuring shapes irrespective of an inclined direction of a side surface without using a complex device configuration, and a shape measurement device probe arranged in the shape measurement device. In the shape measurement device probe, a connecting mechanism for connecting an attachment member and a swinging member includes a supporting point member arranged on the swinging member and a mounting platform arranged on the attachment member, and connects the swinging member to the attachment member so as to be inclinable in any direction. The attachment member and the swinging member are configured such that a movable side member arranged on the swinging member and a fixed side member arranged on the attachment member generate magnetic attraction force in a non-contacting state with respect to each other, where the arm of the swinging member is biased so as to be directed in the vertical direction by the magnetic attraction force. According to this configuration, a side surface shape inclined in any direction of XY directions and substantially parallel to the Z-direction can be measured.

公开(公告)号：US07759763B2

公开(公告)日：2010-07-20

申请号：US12116193

申请日：2008-05-06

申请人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

发明人： Keiichi Yoshizumi ,  Kazuhisa Higuchi ,  Takayuki Nakaji ,  Masami Koketsu ,  Hideki Yasuoka

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/82

CPC分类号： H01L27/0629 ,  H01L21/823462 ,  H01L21/823857 ,  H01L28/20 ,  H01L28/40

摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

摘要翻译： 尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。 在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。 由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

公开(公告)号：US20100011601A1

公开(公告)日：2010-01-21

申请号：US11919557

申请日：2007-05-08

申请人： Takanori Funabashi ,  Keiichi Yoshizumi

发明人： Takanori Funabashi ,  Keiichi Yoshizumi

IPC分类号： G01B5/16

CPC分类号： G01B5/012 ,  G01B7/012 ,  G01B11/007

摘要： There are provided a shape measurement device capable of measuring shapes irrespective of an inclined direction of a side surface without using a complex device configuration, and a shape measurement device probe arranged in the shape measurement device. In the shape measurement device probe, a connecting mechanism for connecting an attachment member and a swinging member includes a supporting point member arranged on the swinging member and a mounting platform arranged on the attachment member, and connects the swinging member to the attachment member so as to be inclinable in any direction. The attachment member and the swinging member are configured such that a movable side member arranged on the swinging member and a fixed side member arranged on the attachment member generate magnetic attraction force in a non-contacting state with respect to each other, where the arm of the swinging member is biased so as to be directed in the vertical direction by the magnetic attraction force. According to this configuration, a side surface shape inclined in any direction of XY directions and substantially parallel to the Z-direction can be measured.

摘要翻译： 提供一种形状测量装置，并且不需要使用复杂的装置结构就能够测量与侧面的倾斜方向无关的形状，以及设置在形状测量装置中的形状测量装置探针。 在形状测量装置探针中，用于连接安装构件和摆动构件的连接机构包括布置在摆动构件上的支撑构件和布置在安装构件上的安装平台，并且将摆动构件连接到附接构件，以便 可以在任何方向倾斜。 安装构件和摆动构件被构造成使得设置在摆动构件上的可动侧构件和布置在附接构件上的固定侧构件相对于彼此以非接触状态产生磁吸引力，其中臂 摆动构件通过磁吸引力被偏置成在垂直方向上被引导。 根据该结构，能够测定沿XY方向的任意方向和Z方向大致平行的侧面形状。

公开(公告)号：US07592669B2

公开(公告)日：2009-09-22

申请号：US11776380

申请日：2007-07-11

申请人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

发明人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

IPC分类号： H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/456 ,  H01L29/7835

摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

摘要翻译： 为了抑制或防止在具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应的目的，n +型半导体区域具有与p +型半导体区域相反的导通类型，用于源极和漏极的高电压 击穿电压pMIS设置在高击穿电压pMIS的沟道区域的两端，栅极宽度方向的沟槽型隔离部分之间的边界区域以及与p-型半导体隔开的位置处的半导体衬底 具有高的击穿电压pMIS的场弛豫功能的区域，以便不与p型半导体区域（特别是在漏极侧）接触。 n +型半导体区域延伸到比沟槽型隔离部分更深的位置。

公开(公告)号：US07514749B2

公开(公告)日：2009-04-07

申请号：US12122717

申请日：2008-05-18

申请人： Kunihiko Kato ,  Masami Koketsu ,  Shigeya Toyokawa ,  Keiichi Yoshizumi ,  Hideki Yasuoka ,  Yasuhiro Takeda

发明人： Kunihiko Kato ,  Masami Koketsu ,  Shigeya Toyokawa ,  Keiichi Yoshizumi ,  Hideki Yasuoka ,  Yasuhiro Takeda

IPC分类号： H01L23/62

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0629 ,  H01L28/40

摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.

摘要翻译： 提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。 预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和 在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。 可以减少半导体集成电路器件的制造步骤的数量。

公开(公告)号：US20080258236A1

公开(公告)日：2008-10-23

申请号：US11776380

申请日：2007-07-11

申请人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

发明人： Hideki Yasuoka ,  Keiichi Yoshizumi ,  Masami Koketsu

IPC分类号： H01L27/088

CPC分类号： H01L29/66659 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/456 ,  H01L29/7835

摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.

摘要翻译： 为了抑制或防止具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应，n + +型半导体区域具有与p < 用于高击穿电压pMIS的源极和漏极的+ 型半导体区域设置在高频沟道区域的栅极宽度方向的两端的沟槽型隔离部分之间的边界区域中 击穿电压pMIS和半导体衬底在高击穿电压pMIS的每个具有场弛豫功能的位置间隔开的位置处，以便不接触p型 - 型半导体区域（特别是在漏极侧）。 n + +型半导体区域延伸到比沟槽型隔离部分更深的位置。

公开(公告)号：US06623986B2

公开(公告)日：2003-09-23

申请号：US09984465

申请日：2001-10-30

申请人： Kiyoshi Ogata ,  Kazuhiko Horikoshi ,  Kazufumi Suenaga ,  Hisayuki Kato ,  Keiichi Yoshizumi ,  Masahito Yamazaki

发明人： Kiyoshi Ogata ,  Kazuhiko Horikoshi ,  Kazufumi Suenaga ,  Hisayuki Kato ,  Keiichi Yoshizumi ,  Masahito Yamazaki

IPC分类号： H01L2100

CPC分类号： H01L28/57 ,  H01L27/1203

摘要： Along life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing a plurality of degradation preventive layers on an upper protection electrode and an upper electrode 8 and a degradation preventive layer at the boundary of ferroelectric layer 7/electrodes 6, 8, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer 7/upper electrode 8. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of ferroelectric characteristic to attain a long life ferroelectric memory device.

摘要翻译： 通过在铁氧体层7 /电极6的边界上的上保护电极和上电极8以及降解防止层上设置多个防结层，可以获得使用薄铁电体膜电容器作为记忆电容器的寿命铁电存储器件 或者提供在铁电层7 /上电极8的边界处减少改性层的步骤。这提供了一种薄铁电薄膜电容器，其经受较少的疲劳和压印，并且具有较低的铁电特性降低以达到 长寿命铁电存储器件。

公开(公告)号：US5610856A

公开(公告)日：1997-03-11

申请号：US610185

申请日：1996-03-04

申请人： Keiichi Yoshizumi ,  Satoru Haga ,  Shuji Ikeda ,  Kiichi Makuta ,  Takeshi Fukazawa

发明人： Keiichi Yoshizumi ,  Satoru Haga ,  Shuji Ikeda ,  Kiichi Makuta ,  Takeshi Fukazawa

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L27/1112 ,  Y10S257/904

摘要： An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.

摘要翻译： 当使用与衬垫层相同层的Al布线精细地构成用于分流的接地电压线时，由于采用这样的布局，使得电阻增加和电迁移阻抗的降低最小化： 在连接到互补数据线的一个（数据线）的衬垫层中的连接孔24,26的布置以及连接到互补数据线的另一个（数据线条）的焊盘层中的连接孔的布置是： 沿着互补数据线延伸的方向在SRAM中的每两位存储器单元互相反相。