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公开(公告)号：US20130248880A1
公开(公告)日：2013-09-26
申请号：US13601457
申请日：2012-08-31
申请人： Keiko ARIYOSHI , Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
发明人： Keiko ARIYOSHI , Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
IPC分类号： H01L29/788 , H01L29/66
CPC分类号： H01L29/7889 , H01L29/045 , H01L29/1608 , H01L29/407 , H01L29/42368 , H01L29/66068 , H01L29/66825 , H01L29/7813
摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode.
摘要翻译： 根据一个实施例，半导体器件包括第一，第二，第三和第四半导体区域，控制电极，浮置电极和绝缘膜。 第一区域包含碳化硅。 第二区域设置在第一区域上并且包含碳化硅。 第三区域设置在第二区域上并且包含碳化硅。 第四区域设置在第三区域并且包含碳化硅。 控制电极设置在形成在第四，第三和第二区域中的沟槽中。 浮置电极设置在控制电极和沟槽的底表面之间。 绝缘膜设置在沟槽和控制电极之间，沟槽和浮动电极之间以及控制电极和浮动电极之间。
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公开(公告)号：US09029869B2
公开(公告)日：2015-05-12
申请号：US13034264
申请日：2011-02-24
申请人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
发明人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
IPC分类号： H01L29/15 , H01L29/739 , H01L29/10 , H01L29/66
CPC分类号： H01L29/7395 , H01L29/1033 , H01L29/66333
摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.
摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅极绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。
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公开(公告)号：US20100308343A1
公开(公告)日：2010-12-09
申请号：US12846400
申请日：2010-07-29
申请人： Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
发明人： Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
CPC分类号： H01L29/7802 , H01L21/0465 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7816
摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.
摘要翻译： 根据实施例，半导体器件包括第一或第二导电类型的SiC衬底。 第一导电类型的SiC层形成在基板的前表面上，第二导电类型的第一SiC区域形成在SiC层上，第一导电类型的第二SiC区域形成在 第一SiC区域，在SiC层，第二SiC区域和介于SiC层和第二SiC区域之间的第一SiC区域的表面上连续地形成栅极电介质，在栅极电介质上形成栅电极， 第一电极嵌入在第一SiC区域与第二SiC区域相邻的部分中选择性地形成的沟槽中，并且在衬底的背面上形成第二电极。
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公开(公告)号：US08686436B2
公开(公告)日：2014-04-01
申请号：US13600532
申请日：2012-08-31
申请人： Hiroshi Kono , Takashi Shinohe , Takuma Suzuki , Johji Nishio
发明人： Hiroshi Kono , Takashi Shinohe , Takuma Suzuki , Johji Nishio
IPC分类号： H01L29/16
CPC分类号： H01L29/1608 , H01L29/0696 , H01L29/086 , H01L29/1045 , H01L29/1095 , H01L29/7395 , H01L29/7802
摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, an insulating film, a control electrode, a first electrode, and a second electrode. The first semiconductor region includes silicon carbide, and has a first portion. The second semiconductor region is provided on the first semiconductor region, and includes silicon carbide. The third semiconductor region and the fourth semiconductor region are provided on the second semiconductor region, and includes silicon carbide. The electrode is provided on the film. The second semiconductor region has a first region and a second region. The first region contacts with the third semiconductor region and the fourth semiconductor region. The second region contacts with the first portion. The impurity concentration of the first region is higher than an impurity concentration of the second region.
摘要翻译： 根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域，第四半导体区域，绝缘膜，控制电极，第一电极和第二电极。 第一半导体区域包括碳化硅，并且具有第一部分。 第二半导体区域设置在第一半导体区域上，并且包括碳化硅。 第三半导体区域和第四半导体区域设置在第二半导体区域上，并且包括碳化硅。 电极设在膜上。 第二半导体区域具有第一区域和第二区域。 第一区域与第三半导体区域和第四半导体区域接触。 第二区域与第一部分接触。 第一区域的杂质浓度高于第二区域的杂质浓度。
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公开(公告)号：US08012837B2
公开(公告)日：2011-09-06
申请号：US12716403
申请日：2010-03-03
申请人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
发明人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L21/336 , H01L21/425 , H01L21/265
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/0495 , H01L21/30604 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/66143 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。
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公开(公告)号：US20120056195A1
公开(公告)日：2012-03-08
申请号：US13034264
申请日：2011-02-24
申请人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
发明人： Hiroshi Kono , Takashi Shinohe , Chiharu Ota , Makoto Mizukami , Takuma Suzuki , Johji Nishio
IPC分类号： H01L29/161
CPC分类号： H01L29/7395 , H01L29/1033 , H01L29/66333
摘要： One embodiment of a semiconductor device includes: a silicon carbide substrate including first and second principal surfaces; a first-conductive-type silicon carbide layer on the first principal surface; a second-conductive-type first silicon carbide region at a surface of the first silicon carbide layer; a first-conductive-type second silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type third silicon carbide region at the surface of the first silicon carbide region; a second-conductive-type fourth silicon carbide region formed between the first silicon carbide region and the second silicon carbide region, and having an impurity concentration higher than that of the first silicon carbide region; a gate insulator; a gate electrode formed on the gate insulator; an inter-layer insulator; a first electrode connected to the second silicon carbide region and the third silicon carbide region; and a second electrode on the second principal surface.
摘要翻译： 半导体器件的一个实施例包括：包含第一和第二主表面的碳化硅衬底; 第一主表面上的第一导电型碳化硅层; 在所述第一碳化硅层的表面处的第二导电型第一碳化硅区域; 在第一碳化硅区域的表面处的第一导电型第二碳化硅区域; 在第一碳化硅区域的表面处的第二导电型第三碳化硅区域; 在第一碳化硅区域和第二碳化硅区域之间形成的杂质浓度高于第一碳化硅区域的第二导电型第四碳化硅区域; 栅极绝缘体; 形成在栅绝缘体上的栅电极; 层间绝缘体; 连接到所述第二碳化硅区域和所述第三碳化硅区域的第一电极; 和在第二主表面上的第二电极。
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公开(公告)号：US20110059597A1
公开(公告)日：2011-03-10
申请号：US12716403
申请日：2010-03-03
申请人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
发明人： Johji Nishio , Chiharu Ota , Takuma Suzuki , Hiroshi Kono , Makoto Mizukami , Takashi Shinohe
IPC分类号： H01L21/20
CPC分类号： H01L29/7802 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/0495 , H01L21/30604 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/66143 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device capable of realizing a high yield of a large-scale semiconductor device even when a silicon carbide semiconductor including a defect is used is provided. The method of manufacturing a semiconductor device includes: a step of epitaxially growing a silicon carbide semiconductor layer on a silicon carbide semiconductor substrate; a step of polishing a surface of the silicon carbide semiconductor layer; a step of ion-implanting impurities into the silicon carbide semiconductor layer after the step of polishing; a step of performing heat treatment to activate the impurities; a step of forming a first thermal oxide film on the surface of the silicon carbide semiconductor layer after the step of performing heat treatment; a step of chemically removing the first thermal oxide film; and a step of forming an electrode layer on the silicon carbide semiconductor film.
摘要翻译： 提供了即使当使用包括缺陷的碳化硅半导体时也能够实现大规模半导体器件的高产率的半导体器件的制造方法。 制造半导体器件的方法包括：在碳化硅半导体衬底上外延生长碳化硅半导体层的步骤; 抛光所述碳化硅半导体层的表面的步骤; 在抛光步骤之后将杂质离子注入到碳化硅半导体层中的步骤; 进行热处理以活化杂质的步骤; 在进行热处理的步骤之后，在碳化硅半导体层的表面上形成第一热氧化膜的工序; 化学去除第一热氧化膜的步骤; 以及在所述碳化硅半导体膜上形成电极层的步骤。
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公开(公告)号：US08431974B2
公开(公告)日：2013-04-30
申请号：US12846400
申请日：2010-07-29
申请人： Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
发明人： Takuma Suzuki , Hiroshi Kono , Takashi Shinohe
IPC分类号： H01L29/66
CPC分类号： H01L29/7802 , H01L21/0465 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/42368 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7816
摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.
摘要翻译： 根据实施例，半导体器件包括第一或第二导电类型的SiC衬底。 第一导电类型的SiC层形成在基板的前表面上，第二导电类型的第一SiC区域形成在SiC层上，第一导电类型的第二SiC区域形成在 第一SiC区域，在SiC层，第二SiC区域和介于SiC层和第二SiC区域之间的第一SiC区域的表面上连续地形成栅极电介质，在栅极电介质上形成栅电极， 第一电极嵌入在第一SiC区域与第二SiC区域相邻的部分中选择性地形成的沟槽中，并且在衬底的背面上形成第二电极。
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公开(公告)号：US08686437B2
公开(公告)日：2014-04-01
申请号：US13601408
申请日：2012-08-31
申请人： Hiroshi Kono , Takashi Shinohe , Takuma Suzuki , Johji Nishio
发明人： Hiroshi Kono , Takashi Shinohe , Takuma Suzuki , Johji Nishio
IPC分类号： H01L29/15
CPC分类号： H01L21/0465 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/7395 , H01L29/7802 , H01L29/7827
摘要： According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth, and a fifth semiconductor region, an insulating film, a control electrode, and a first and a second electrode. The first, the second, the third, the fourth and the fifth semiconductor region include silicon carbide. The first semiconductor region has a first impurity concentration, and has a first portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided between the first portion and the second semiconductor region. The fourth semiconductor region is provided between the first portion and the third semiconductor region. The fifth semiconductor region includes a first region provided between the first portion and the second semiconductor region, and has a second impurity concentration higher than the first impurity concentration.
摘要翻译： 根据一个实施例，半导体器件包括第一，第二，第三，第四和第五半导体区域，绝缘膜，控制电极以及第一和第二电极。 第一，第二，第三，第四和第五半导体区域包括碳化硅。 第一半导体区域具有第一杂质浓度，并且具有第一部分。 第二半导体区域设置在第一半导体区域上。 第三半导体区域设置在第二半导体区域上。 第四半导体区域设置在第一部分和第二半导体区域之间。 第四半导体区域设置在第一部分和第三半导体区域之间。 第五半导体区域包括设置在第一部分和第二半导体区域之间的第一区域，并且具有高于第一杂质浓度的第二杂质浓度。
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公开(公告)号：US08569795B2
公开(公告)日：2013-10-29
申请号：US13217472
申请日：2011-08-25
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7813
摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.
摘要翻译： 实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。
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