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18 条记录 (耗时 0.024 秒)

    Method and apparatus for settling and maintaining a DC offset
    1.
    发明授权
    Method and apparatus for settling and maintaining a DC offset 有权
    用于稳定和维持DC偏移的方法和装置

    公开(公告)号：US06225848B1

    公开(公告)日：2001-05-01

    申请号：US09515286

    申请日：2000-02-29

    申请人： Keith A. Tilley ,  Raul Salvi ,  Enrique Ferrer ,  Atif A. Meraj ,  David J. Graham

    发明人： Keith A. Tilley ,  Raul Salvi ,  Enrique Ferrer ,  Atif A. Meraj ,  David J. Graham

    IPC分类号： H03K508

    CPC分类号： H03F1/304 ,  H03F2200/372

    摘要： A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202). When a correction value is obtained, it is applied and held (524) to compensate for the DC offset. When a programming event occurs (534), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.

    摘要翻译： 直流偏移校正回路（200）利用符号位产生器（204），二进制搜索级（206）和数模转换器（208）在其反馈路径中校正增益输入端的直流偏移 阶段（202）。 当获得校正值时，施加和保持（524）以补偿DC偏移。 当发生编程事件（534）时，例如检测DC偏移的增加超过阈值，检测明显的温度变化或时间的流逝，则开始新的DC偏移校正周期。

    Enhanced DC offset correction through bandwidth and clock speed selection
    2.
    发明授权
    Enhanced DC offset correction through bandwidth and clock speed selection 有权
    通过带宽和时钟速度选择增强直流偏移校正

    公开(公告)号：US06356217B1

    公开(公告)日：2002-03-12

    申请号：US09515843

    申请日：2000-02-29

    申请人： Keith A. Tilley ,  Raul Salvi ,  Enrique Ferrer

    发明人： Keith A. Tilley ,  Raul Salvi ,  Enrique Ferrer

    IPC分类号： H03M110

    CPC分类号： H03F1/304

    摘要： A DC offset correction method and apparatus. In a DC offset correction loop (100), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset (138) is used to control a direction in which a digital to analog converter (DAC) (166) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters (130) to permit the binary search to be clocked (180) at a higher clock rate. After the correction is established, the filters (130) are reset to normal operating conditions.

    摘要翻译： DC偏移校正方法和装置。 在DC偏移校正回路（100）中，使用二分搜索程序或任何其他数字或模拟DC偏移校正技术校正DC偏移。 在该二进制搜索例程中，偏移量（138）的符号用于控制数模转换器（DAC）（166）的步进直到DAC的最低有效位被置位的方向。 通过打开基带滤波器（130）的带宽来增强该过程，以允许二进制搜索以更高的时钟速率被计时（180）。 在建立校正之后，将过滤器（130）复位到正常的操作条件。

    Varactor tuning circuit having plural selectable bias voltages
    5.
    发明授权
    Varactor tuning circuit having plural selectable bias voltages 失效
    变容二极管调谐电路具有多个可选偏置电压

    公开(公告)号：US4713631A

    公开(公告)日：1987-12-15

    申请号：US816589

    申请日：1986-01-06

    申请人： Ralph T. Enderby ,  Enrique Ferrer ,  Wayne P. Shepherd

    发明人： Ralph T. Enderby ,  Enrique Ferrer ,  Wayne P. Shepherd

    IPC分类号： H03H5/12 ,  H03B1/00 ,  H03J5/02 ,  H03J5/24 ,  H03L7/099 ,  H03L7/187 ,  H04B1/40 ,  H03B5/08 ,  H03L7/18

    CPC分类号： H03L7/187 ,  H03L7/099 ,  H03B2201/0208 ,  H03L2207/06

    摘要： A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.

    摘要翻译： 可变电容电路包括具有阳极侧和阴极侧的变容二极管。 将一个可变偏置电压施加到一个侧面，并且将多个电压中的一个作为第二偏置电压施加到另一侧以控制变容二极管的电容。 连接到分压网络的电压倍增器电路用于提供多个电压。 解码器响应于用于选择和施加多个电压输出中的一个的输入信号。 可变电容电路用于频率合成器的压控振荡器，用于提供扩展的频率范围。

    Method of driving a class D audio power amplifier using non-overlapping edge drive signals
    6.
    发明授权
    Method of driving a class D audio power amplifier using non-overlapping edge drive signals 失效
    使用非重叠边缘驱动信号驱动D类音频功率放大器的方法

    公开(公告)号：US5729175A

    公开(公告)日：1998-03-17

    申请号：US638626

    申请日：1996-04-26

    申请人： Enrique Ferrer

    发明人： Enrique Ferrer

    IPC分类号： H03F3/217 ,  H03F3/38

    CPC分类号： H03F3/2171 ,  H03F3/2173

    摘要： A method of actuating a plurality of power amplifier devices in an Class D audio switching amplifier (100) using non-overlapping edge drive signals for preventing substantially high current spikes during switching transitions. The method includes actuating and deactuating power amplifier devices within a first complementary power switching device (117) and actuating and deactuating a second complementary power switching device (119) using a plurality of drive signals generated by a non-overlapping driver (107). The method provides that the first complementary power switching device (117) and the second complementary power switching device (119) are switched ON and OFF in a predetermined sequence such that more than one power amplifier device within each complementary power switching pair is prevented from being simultaneously activated. This prevents high current spiking and subsequently high current drain during a switching transition for conserving battery life when used with portable equipment.

    摘要翻译： 一种使用非重叠边缘驱动信号来驱动D类音频切换放大器（100）中的多个功率放大器装置的方法，用于在切换转换期间防止基本上高的电流尖峰。 该方法包括在第一互补功率开关装置（117）内致动和停用功率放大器装置，并且使用由非重叠驱动器（107）产生的多个驱动信号来致动和停用第二互补功率开关装置（119）。 该方法提供了第一互补功率开关装置（117）和第二互补功率开关装置（119）以预定的顺序被接通和断开，使得防止每个互补功率开关对内的多于一个的功率放大装置 同时激活。 这样可以防止在切换转换期间产生高电流尖峰和随之而来的高电流消耗，从而在与便携设备一起使用时节省电池寿命。

    Means and method of enhancing signal resolution and dynamic range extension in a pulse width modulation amplifier
    7.
    发明授权
    Means and method of enhancing signal resolution and dynamic range extension in a pulse width modulation amplifier 失效
    在脉冲宽度调制放大器中增强信号分辨率和动态范围扩展的手段和方法

    公开(公告)号：US5422597A

    公开(公告)日：1995-06-06

    申请号：US251227

    申请日：1994-05-31

    申请人： Robert E. Stengel ,  David L. Muri ,  Enrique Ferrer

    发明人： Robert E. Stengel ,  David L. Muri ,  Enrique Ferrer

    IPC分类号： H03F3/217 ,  H03F3/38

    CPC分类号： H03F3/2173

    摘要： An amplifier (1) used with a pulse width modulated signal which improves the efficiency of a low level input signal comprises two or more switching devices (7,9) with common source/drain or emitter/collector connections. The gates or the bases of the devices are independently driven to optimize the efficiency of the various Rds (on) resistance values of the transistors (61, 63, 65, 89, 91, 93) used in the devices. The amplifier is operated so that during the highest output levels, select switching devices (61, 63, 65) are utilized to reduce in series resistance with the load (13). As output power decreases, devices (89, 91, 93) with higher Rds (on) resistance values are activated by a control signal which greatly improves DC to DC conversion efficiency with improved output voltage resolution, dynamic range and reduced electromagnetic interference potential.

    摘要翻译： 与改善低电平输入信号的效率的脉冲宽度调制信号一起使用的放大器（1）包括具有公共源极/漏极或发射极/集电极连接的两个或多个开关器件（7,9）。 独立地驱动器件的栅极或基极以优化器件中使用的晶体管（61,63,65,89,91,93）的各种Rds（导通）电阻值的效率。 放大器的工作原理是，在最高的输出电平下，选择开关器件（61,63,65）来减少负载（13）的串联电阻。 随着输出功率的降低，具有较高Rds（on）电阻值的器件（89,91,93）由控制信号激活，通过改进的输出电压分辨率，动态范围和降低的电磁干扰电位，极大地提高了DC至DC转换效率。

    Method of encoding and decoding data signals
    9.
    发明授权
    Method of encoding and decoding data signals 失效
    数据信号的编码和解码方法

    公开(公告)号：US4686528A

    公开(公告)日：1987-08-11

    申请号：US843876

    申请日：1986-03-26

    申请人： Enrique Ferrer ,  Charles M. Schlosser

    发明人： Enrique Ferrer ,  Charles M. Schlosser

    IPC分类号： G06F3/12 ,  G06F13/42 ,  H04L25/48 ,  H04L25/49 ,  G08B5/22

    CPC分类号： H04L25/4923 ,  G06F13/4269 ,  G06F3/1293

    摘要： In a multiple state data signal, a first and second state are equated to logic states while a third state is designated as a read state. The read state and one of the two logic states are alternately generated so that each logic state is immediately preceeded by a read signal which may be utilized to tell the peripheral that a valid bit of data follows.

    摘要翻译： 在多状态数据信号中，第一状态和第二状态等于逻辑状态，而第三状态被指定为读取状态。 交替地产生读取状态和两个逻辑状态中的一个，使得每个逻辑状态紧接在读取信号之前，该读取信号可用于告诉外围设备有效的数据位。

    INTEGRATED CIRCUIT WITH IMPROVED SIGNAL NOISE ISOLATION AND METHOD FOR IMPROVING SIGNAL NOISE ISOLATION
    10.
    发明申请
    INTEGRATED CIRCUIT WITH IMPROVED SIGNAL NOISE ISOLATION AND METHOD FOR IMPROVING SIGNAL NOISE ISOLATION 有权
    具有改进的信号噪声隔离的集成电路和用于改善信号噪声隔离的方法

    公开(公告)号：US20060267133A1

    公开(公告)日：2006-11-30

    申请号：US11142433

    申请日：2005-05-31

    申请人： Suman Banerjee ,  Enrique Ferrer ,  Olin Hartin ,  Radu Secareanu

    发明人： Suman Banerjee ,  Enrique Ferrer ,  Olin Hartin ,  Radu Secareanu

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0248 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is connected to an N well ring (124) of the first noise sensitive circuit (120) to collect noise from the substrate (110) and isolate the circuit from the P well region (112). A ground protected pad (304) is connected to an isolated P well (126) of a first noise sensitive circuit (120). The ground pad (304) collects noise from the isolated P well (126) and sends it to ground. A dedicated ground isolation pad (306) is connected to a P well ring (224) of a second noise sensitive circuit (220). The dedicated ground isolation pad (306) collects noise from the P well ring (224) and sends it to ground. The dedicated ground isolation pad (306) and the ground pad (304) collect noise that would normally propagate between the first and second noise sensitive circuits (120, 220) and additional circuits that share the same substrate (110).

    摘要翻译： 一种片上系统（SOC）（100）以及分离SOC中的噪声的方法，包括多个噪声敏感电路块（120,220）和ESD保护焊盘（302,304,306,308,310,312,312） 和314）。 VDD隔离焊盘（302）连接到第一噪声敏感电路（120）的N阱环（124），以从基板（110）收集噪声，并将电路与P阱区域（112）隔离。 接地保护焊盘（304）连接到第一噪声敏感电路（120）的隔离P阱（126）。 接地焊盘（304）从隔离的P阱（126）收集噪声并将其发送到地面。 专用接地隔离垫（306）连接到第二噪声敏感电路（220）的P阱环（224）。 专用接地隔离垫（306）从P阱环（224）收集噪声并将其发送到地面。 专用接地隔离焊盘（306）和接地焊盘（304）收集正常地在第一和第二噪声敏感电路（120,220）之间传播的噪声以及共享相同衬底（110）的附加电路。