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    Overlay and CD process window structure
    3.
    发明授权
    Overlay and CD process window structure 失效
    覆盖和CD过程窗口结构

    公开(公告)号：US06967709B2

    公开(公告)日：2005-11-22

    申请号：US10707198

    申请日：2003-11-26

    申请人： Daniel J. Mellinger ,  Timothy C. Milmore ,  Matthew C. Nicholls

    发明人： Daniel J. Mellinger ,  Timothy C. Milmore ,  Matthew C. Nicholls

    IPC分类号： G03F7/20 ,  G03B27/42 ,  G03B27/32 ,  G03F9/00

    CPC分类号： G03F7/70625 ,  G03F7/70633

    摘要： The present invention provides photolithographic device and method for optimizing the photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions. This process enables the user to determine the lithographic process window for critical dimension and overlay on a single chip using electrical test structures.

    摘要翻译： 本发明提供了用于优化光刻工艺窗口的光刻设备和方法。 光刻装置包括基板; 以及具有辐射能透明部分和辐射能阻挡部分的图案层，其中图案层具有变化的覆盖层的特征。 覆盖公差通过改变图案的特征的不对准来确定。 光刻装置是光罩。 用于确定最佳光刻处理窗口的方法包括将晶片的一部分暴露于由掩模版产生的图案，该图案具有产生多个光刻条件的变化的覆盖层，其中每个光刻条件具有覆盖公差; 并且跨越晶片的剩余部分使掩模版步进，其中每个步骤将晶片的其它区域暴露于产生多个光刻条件的图案。 该过程使用户能够使用电气测试结构来确定关键尺寸的光刻工艺窗口并覆盖在单个芯片上。

    Overlay and CD process window structure
    4.
    发明授权
    Overlay and CD process window structure 失效
    覆盖和CD过程窗口结构

    公开(公告)号：US07538344B2

    公开(公告)日：2009-05-26

    申请号：US11028888

    申请日：2005-01-04

    申请人： Daniel J. Mellinger ,  Timothy C. Milmore ,  Matthew C. Nicholls

    发明人： Daniel J. Mellinger ,  Timothy C. Milmore ,  Matthew C. Nicholls

    IPC分类号： G03F9/00 ,  H01L23/58

    CPC分类号： G03F7/70625 ,  G03F7/70633

    摘要： The present invention provides photolithographic device and method for photolithography process window. The photolithography device comprises a substrate; and a pattern layer having radiant energy transparent portions and radiant energy blocking portions, where the pattern layer has features with a varying overlay. The overlay tolerance is determined by varying the misalignment the features of the pattern. The photolithography device is a reticle. The method for determining an optimum photolithography process window comprises exposing a portion of a wafer to a pattern produced by a reticle, the pattern having a varying overlay that produces multiple photolithography conditions, wherein each photolithography condition has an overlay tolerance; and stepping the reticle across a remaining portion of the wafer, where each step exposes an other region of the wafer to the pattern producing multiple photolithography conditions. This process enables the user to determine the lithographic process window for critical dimension and overlay on a single chip using electrical test structures.

    摘要翻译： 本发明提供了光刻工艺窗口的光刻设备和方法。 光刻装置包括基板; 以及具有辐射能透明部分和辐射能阻挡部分的图案层，其中图案层具有变化的覆盖层的特征。 覆盖公差通过改变图案的特征的不对准来确定。 光刻装置是光罩。 用于确定最佳光刻处理窗口的方法包括将晶片的一部分暴露于由掩模版产生的图案，该图案具有产生多个光刻条件的变化的覆盖层，其中每个光刻条件具有覆盖公差; 并且跨越晶片的剩余部分使掩模版步进，其中每个步骤将晶片的其它区域暴露于产生多个光刻条件的图案。 该过程使用户能够使用电气测试结构来确定关键尺寸的光刻工艺窗口并覆盖在单个芯片上。

    HDP-based ILD capping layer
    5.
    发明授权
    HDP-based ILD capping layer 有权
    基于HDP的ILD覆盖层

    公开(公告)号：US07138717B2

    公开(公告)日：2006-11-21

    申请号：US10904827

    申请日：2004-12-01

    申请人： Yun-Yu Wang ,  Richard A. Conti ,  Chung-Ping Eng ,  Matthew C. Nicholls

    发明人： Yun-Yu Wang ,  Richard A. Conti ,  Chung-Ping Eng ,  Matthew C. Nicholls

    IPC分类号： H01L29/40

    CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53228 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.

    摘要翻译： 一种覆盖氮化物叠层，可以防止蚀刻渗透到HDP氮化物，同时保持在Cu顶部的HDP氮化物的电迁移效果。 在一个实施例中，堆叠包括第一层HDP氮化物和设置在第一层上的Si-C-H化合物的第二层。 Si-C-H化合物例如是BLoK或N-BLoK（Si-C-H-N），并且选自在通孔RIE期间具有高选择性的一组材料，使得来自下一个布线层的RIE化学不会穿透。 碳氮是关键要素。 在另一个实施例中，堆叠包括第一层HDP氮化物，随后是第二层UVN（等离子体氮化物），以及包含设置在第二层上的HDP氮化物的第三层。

    Mask/wafer control structure and algorithm for placement
    6.
    发明授权
    Mask/wafer control structure and algorithm for placement 失效
    掩模/晶片控制结构和放置算法

    公开(公告)号：US06766507B2

    公开(公告)日：2004-07-20

    申请号：US10121811

    申请日：2002-04-12

    申请人： James A. Bruce ,  Stephen E. Knight ,  Joshua J. Krueger ,  Matthew C. Nicholls ,  Jed H. Rankin

    发明人： James A. Bruce ,  Stephen E. Knight ,  Joshua J. Krueger ,  Matthew C. Nicholls ,  Jed H. Rankin

    IPC分类号： G06F1750

    CPC分类号： G03F7/70625 ,  G03F7/70433 ,  G03F7/70683

    摘要： A mask/wafer control structure and an algorithm for placement thereof provide for data placement of measurement control structures, called a PLS, Process limiting Structure, on a mask and a plurality of chips on the wafer which provide for tighter control of both mask manufacture and wafer production by providing the most critical design structures for measurement during creation of the mask, and in the photolithography and etch processes. The PLS structures are located at multiple locations throughout the chip, and so they receive the same data preparation as the chip, and measurement tools are able to measure the same features at each fabrication step from fabrication of the mask to final formation of the etched features. Manufacturing control and the interlock between the wafer fabrication and the mask fabrication are enhanced, allowing for improved quality of the final product.

    摘要翻译： 掩模/晶片控制结构及其放置算法提供在晶片上的掩模和多个芯片上的称为PLS，过程限制结构的测量控制结构的数据放置，其提供对掩模制造和 在制作掩模期间以及在光刻和蚀刻工艺中提供用于测量的最关键的设计结构的晶片生产。 PLS结构位于整个芯片的多个位置，因此它们接收与芯片相同的数据准备，并且测量工具能够在从制造掩模到最终形成蚀刻特征的每个制造步骤处测量相同的特征 。 增强制造控制和晶片制造与掩模制造之间的互锁，从而允许最终产品的质量提高。

    Method and system for determining overlay tolerance
    7.
    发明授权
    Method and system for determining overlay tolerance 失效
    确定重叠公差的方法和系统

    公开(公告)号：US06716559B2

    公开(公告)日：2004-04-06

    申请号：US10016211

    申请日：2001-12-13

    申请人： Robert K. Leidy ,  Timothy C. Milmore ,  Matthew C. Nicholls

    发明人： Robert K. Leidy ,  Timothy C. Milmore ,  Matthew C. Nicholls

    IPC分类号： G03F900

    CPC分类号： G03F7/70633 ,  Y10S438/975

    摘要： A method and system for determining overlay tolerances. The method comprises the steps of exposing wafers at different critical dimensions (preferably, above, below, and at optimum image size); and varying the overlay across each wafer, preferably by intentionally increasing the magnification. Functional yield data are used to determine the overlay tolerance for each of the image sizes. The present invention, thus, studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.

    摘要翻译： 一种用于确定覆盖公差的方法和系统。 该方法包括以不同临界尺寸（优选高于，低于，最佳图像尺寸）曝光晶片的步骤; 并且优选地通过有意地增加放大倍数来改变跨每个晶片的覆盖层。 功能产量数据用于确定每个图像尺寸的覆盖公差。 因此，本发明研究图像尺寸和特征不对准的相互作用。 在本发明之前，获得这些信息的唯一方法是处理大量的批次，并产生图像尺寸和对准与产量的趋势。 本发明通过基于来自单个批次的产量数据确定覆盖公差来解决该问题。 然后可以基于对未对准最敏感的区域/特征的故障分析，改变设计或覆盖限制（或放松）。

    Multi-run selective pattern and etch wafer process
    8.
    发明授权
    Multi-run selective pattern and etch wafer process 失效
    多运行选择性图案和蚀刻晶圆工艺

    公开(公告)号：US07060626B2

    公开(公告)日：2006-06-13

    申请号：US10604087

    申请日：2003-06-25

    申请人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

    发明人： Kenneth A. Bandy ,  Vincent J. Carlos ,  Mark D. Levy ,  Sara L. Lucas ,  Timothy C. Milmore ,  Matthew C. Nicholls ,  Jason Nowakowski

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/31144

    摘要： A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.

    摘要翻译： 一种用于形成半导体晶片的方法，包括将第一图案化抗蚀剂施加到晶片的至少一个第一预定区域，其中所述晶片的所述至少一个第一预定区域被所述第一图案化抗蚀剂保护并且所述晶片的第一剩余部分 不受所述第一图案化抗蚀剂的保护; 蚀刻所述晶片的未被所述第一图案抗蚀剂保护的所述第一剩余部分; 从所述晶片剥离第一图案抗蚀剂; 将第二图案化抗蚀剂施加到所述晶片的至少一个第二预定区域，其中所述晶片的所述至少一个第二预定区域被第二图案化抗蚀剂保护，并且第二剩余部分不被所述第二图案化抗蚀剂保护; 蚀刻不被所述第二图案化抗蚀剂保护的所述第二剩余部分; 以及从所述晶片剥离所述第二图案化抗蚀剂。