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22 条记录 (耗时 0.022 秒)

    Aggregatable connectivity
    1.
    发明授权
    Aggregatable connectivity 有权
    可聚合连接

    公开(公告)号：US07415032B2

    公开(公告)日：2008-08-19

    申请号：US10294180

    申请日：2002-11-13

    申请人： Ken Drottar ,  David S. Dunning ,  Andrew Martwick ,  Zale Schoenborn ,  Scott T. Gardiner

    发明人： Ken Drottar ,  David S. Dunning ,  Andrew Martwick ,  Zale Schoenborn ,  Scott T. Gardiner

    IPC分类号： H04J3/16

    CPC分类号： H04L1/22

    摘要： A first device and a second device, each coupled to one or more signal paths, attempting to transmit symbols over one or more of the signal paths, identifying one or more signal paths over each of which each device is able to transmit a symbol to the other device and over which each device is able to receive a symbol from the other device, and enrolling the identified signal paths into an aggregation of signal paths operable to provide for communication between the devices.

    摘要翻译： 每个耦合到一个或多个信号路径的第一设备和第二设备尝试通过一个或多个信号路径发送符号，识别每个设备能够将符号传输到每个信号路径上的一个或多个信号路径 每个设备能够从其他设备接收符号，并且将所识别的信号路径注册到可用于提供设备之间的通信的信号路径的聚合中。

    Asynchronous coupling and decoupling of chips
    2.
    发明授权
    Asynchronous coupling and decoupling of chips 有权

    公开(公告)号：US06906549B2

    公开(公告)日：2005-06-14

    申请号：US10334735

    申请日：2002-12-31

    申请人： Theodore Zale Schoenborn ,  Andrew Martwick

    发明人： Theodore Zale Schoenborn ,  Andrew Martwick

    IPC分类号： H04L25/45 ,  H03K17/16

    CPC分类号： H04L25/45

    摘要： In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

    Power delivery noise cancellation mechanism
    3.
    发明授权
    Power delivery noise cancellation mechanism 失效
    电力输送噪声消除机制

    公开(公告)号：US07109755B2

    公开(公告)日：2006-09-19

    申请号：US10974220

    申请日：2004-10-27

    申请人： Dmitriy S. Garmatyuk ,  Christopher D. Loental ,  Andrew Martwick

    发明人： Dmitriy S. Garmatyuk ,  Christopher D. Loental ,  Andrew Martwick

    IPC分类号： H03K19/0175

    CPC分类号： H04L25/028 ,  H03K17/162

    摘要： An integrated circuit is disclosed. The integrated circuit includes a power delivery network (PDN), a first voltage rail coupled to the PDN, an input/output (I/O) buffer coupled to the first voltage rail and a driver coupled to the I/O buffer. The driver transmits a current waveform to the I/O buffer whenever a switching event occurs at the I/O buffer.

    摘要翻译： 公开了一种集成电路。 集成电路包括电力输送网络（PDN），耦合到PDN的第一电压轨，耦合到第一电压轨的输入/输出（I / O）缓冲器和耦合到I / O缓冲器的驱动器。 每当I / O缓冲区发生切换事件时，驱动程序将电流波形发送到I / O缓冲区。

    System for managing input/output address accesses at a bridge/memory controller
    5.
    发明授权
    System for managing input/output address accesses at a bridge/memory controller 失效
    用于管理桥/存储器控制器处的输入/输出地址访问的系统

    公开(公告)号：US6145030A

    公开(公告)日：2000-11-07

    申请号：US49829

    申请日：1998-03-27

    申请人： Andrew Martwick

    发明人： Andrew Martwick

    IPC分类号： G06F12/08 ,  G06F13/24 ,  G06F12/10 ,  G06F13/10 ,  G06F13/12 ,  G06F13/14

    CPC分类号： G06F13/24 ,  G06F12/0866

    摘要： An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.

    摘要翻译： 一种装置，包括：输入/输出（I / O）地址验证单元，确定从处理器接收到的I / O地址是否被保护。 中断发生器耦合到I / O地址验证单元。 如果I / O地址被保护，中断发生器将产生一个中断。 中断记录器耦合到地址验证单元。 中断记录器记录中断的原因。

    Asynchronous coupling and decoupling of chips
    6.
    发明申请
    Asynchronous coupling and decoupling of chips 有权
    芯片的异步耦合和去耦

    公开(公告)号：US20050231232A1

    公开(公告)日：2005-10-20

    申请号：US11152268

    申请日：2005-06-13

    申请人： Theodore Schoenborn ,  Andrew Martwick

    发明人： Theodore Schoenborn ,  Andrew Martwick

    IPC分类号： H04L25/45 ,  H03K17/16

    CPC分类号： H04L25/45

    摘要： In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

    摘要翻译： 在一些实施例中，芯片包括第一和第二节点，可变电压源以及发射器和控制电路。 发射机包括耦合到第一和第二节点的驱动器以及分别耦合在第一和第二节点之间的第一和第二电阻结构以及可变电压源。 控制电路选择第一和第二电阻结构的阻抗水平，并通过互连检测远程接收器与发射机的耦​​合，并检测远端接收机与发射机的去耦合。 描述和要求保护其他实施例。

    Programmable measurement mode for a serial point to point link
    7.
    发明申请
    Programmable measurement mode for a serial point to point link 有权
    串行点对点链接的可编程测量模式

    公开(公告)号：US20050154946A1

    公开(公告)日：2005-07-14

    申请号：US10750034

    申请日：2003-12-31

    申请人： Suneel Mitbander ,  Cass Blodgett ,  Andrew Martwick ,  Lyonel Renaud ,  Theodore Schoenborn

    发明人： Suneel Mitbander ,  Cass Blodgett ,  Andrew Martwick ,  Lyonel Renaud ,  Theodore Schoenborn

    IPC分类号： G06F11/267 ,  G01R31/28

    CPC分类号： G06F11/221 ,  G01R31/31716

    摘要： A serial point to point link that communicatively couples an integrated circuit (IC) device to another IC device is initialized by transferring a training sequence of symbols over the link. Registers of the IC device are programmed, to set a symbol data pattern and configure a lane transmitter for the link. A start bit in a register of the IC device is programmed, to request that the link be placed in a measurement mode. In this mode, the IC device instructs the other IC device to enter a loopback mode for the link. The IC device transmits a sequence of test symbols over the link and evaluates a loopback version of the sequence for errors. The sequence of test symbols have a data pattern, and are transmitted, as configured by the registers. Other embodiments are also described and claimed.

    摘要翻译： 将集成电路（IC）设备通信耦合到另一个IC设备的串行点对点链路通过在链路上传送符号的训练序列来初始化。 对IC器件的寄存器进行编程，设置符号数据模式并为链路配置通道发送器。 对IC器件的寄存器中的起始位进行编程，要求将链路置于测量模式。 在该模式中，IC装置指示其他IC装置输入链路的环回模式。 IC设备通过链路发送测试符号序列，并评估序列的环回版本的错误。 测试符号序列具有数据模式，并由寄存器配置发送。 还描述和要求保护其他实施例。

    Autodetection of a PCI express device operating at a wireless RF mitigation frequency
    10.
    发明申请
    Autodetection of a PCI express device operating at a wireless RF mitigation frequency 有权
    自动检测以无线RF减轻频率工作的PCI Express设备

    公开(公告)号：US20060143338A1

    公开(公告)日：2006-06-29

    申请号：US11026968

    申请日：2004-12-29

    申请人： Mikal Hunsaker ,  Karthi Vadivelu ,  Andrew Martwick

    发明人： Mikal Hunsaker ,  Karthi Vadivelu ,  Andrew Martwick

    IPC分类号： G06F3/06

    CPC分类号： G06F13/4295 ,  G06F2213/0026 ,  H04L7/10

    摘要： A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

    摘要翻译： 描述了检测符合PCI Express的端点设备的计算机系统。 具体地，计算机系统以第一频率对发射和接收电路进行计时，并启动训练序列。 如果端点设备以第一个频率成功列车，则端点设备符合PCI Express标准。 否则，计算机系统以第二频率发起另一训练序列。