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公开(公告)号：US5592111A
公开(公告)日：1997-01-07
申请号：US355859
申请日：1994-12-14
CPC分类号： G06F11/0757 , G06F11/076
摘要： A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.
摘要翻译： 用于集成电路的调速器，其防止集成电路在选定频率之上的操作。 调速器产生频率参考，并将频率参考值与对集成电路进行时钟的外部时钟信号的频率进行比较。 作为比较的结果，如果输入时钟信号的频率大于频率参考值，则集成电路的操作被中断。
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公开(公告)号：US20060131070A1
公开(公告)日：2006-06-22
申请号：US11014134
申请日：2004-12-16
申请人： Hong Wong , Alexander Waizman , Hue Lam
发明人： Hong Wong , Alexander Waizman , Hue Lam
IPC分类号： H05K1/11
CPC分类号： G06F1/26 , H05K1/0231 , H05K1/0262 , H05K1/0263 , H05K1/18 , H05K2201/10272 , H05K2201/1053
摘要： According to one embodiment, a system is disclosed. The system includes a power supply a printed circuit board (PCB). The PCB includes a voltage regulator and a bus bar to couple power from the power supply to the voltage regulator
摘要翻译： 根据一个实施例，公开了一种系统。 该系统包括一个印刷电路板（PCB）的电源。 PCB包括电压调节器和汇流条，用于将来自电源的电力耦合到电压调节器
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3.发明授权Delay line loop for on-chip clock synthesis with zero skew and 50% duty cycle 失效延迟线路环路，用于零偏移和50％占空比的片上时钟合成
公开(公告)号：US5410263A
公开(公告)日：1995-04-25
申请号：US023673
申请日：1993-02-26
申请人： Alexander Waizman
发明人： Alexander Waizman
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135 , H03K2005/00104 , H03K2005/00195 , H04L7/033
摘要： In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having a frequency that is equal to, or is a submultiple of, the synthesized internal clock. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference clock duty cycle. Synchronization of the two clocks is achieved by a delay-line-loop using a voltage controlled delay line with a nominal half period delay of the synthesized clock. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and the inverted synthesized clock. This second loop drives the voltage controlled delay line with the synthesized internal clock signal. The integrated circuit clock synthesizer is intended to operate as an integral part of a microprocessor or a peripheral unit operating in a system having a common external reference clock.
摘要翻译： 在用于合成50％占空比内部时钟的集成电路中，内部时钟与零相位差相对于具有等于或者是合成内部时钟的倍数的外部参考时钟同步。 合成波形的占空比相对于参考时钟占空比是固定的和不变的。 通过使用具有合成时钟的标称半周期延迟的电压控制延迟线的延迟线路环来实现两个时钟的同步。 通过第二个控制回路实现50％占空比，其具有参考和反相合成时钟的输入。 该第二回路利用合成的内部时钟信号驱动电压控制的延迟线。 集成电路时钟合成器旨在作为在具有公共外部参考时钟的系统中操作的微处理器或外围单元的组成部分。
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4.发明授权Delay line loop for 1X on-chip clock generation with zero skew and 50% duty cycle 失效延迟线路环路，用于零偏移和50％占空比的1X片上时钟生成
公开(公告)号：US5317202A
公开(公告)日：1994-05-31
申请号：US890038
申请日：1992-05-28
申请人： Alexander Waizman
发明人： Alexander Waizman
CPC分类号： H03L7/0812 , H03K5/133 , H03K5/135 , H03K2005/00104 , H03K2005/00195 , H04L7/033
摘要： In an integrated circuit for synthesizing a 50% duty cycle internal clock, the internal clock is synchronized with zero phase difference with respect to an external reference clock having the same frequency. The duty cycle of the synthesized waveform is fixed and invariant with respect to the reference clock duty cycle. Synchronization of the two clocks is achieved by a delay-line-loop using an inverting voltage controlled delay line with a nominal half period delay. The 50% duty cycle is achieved by a second control loop that has as its input both the reference and synthesized clock. This second loop also shares the voltage controlled delay line with the delay-line-loop.
摘要翻译： 在用于合成50％占空比内部时钟的集成电路中，内部时钟相对于具有相同频率的外部参考时钟与零相位差同步。 合成波形的占空比相对于参考时钟占空比是固定的和不变的。 通过使用具有标称半周期延迟的反相电压控制延迟线的延迟线路环来实现两个时钟的同步。 通过第二个控制回路实现50％占空比，其具有参考和合成时钟的输入。 该第二回路也与延迟线环路共享电压控制的延迟线。
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