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公开(公告)号：US5592111A
公开(公告)日：1997-01-07
申请号：US355859
申请日：1994-12-14
CPC分类号： G06F11/0757 , G06F11/076
摘要： A speed governor for an integrated circuit which prevents the operation of the integrated circuit above a selected frequency. The speed governor generates a frequency reference and compares the frequency reference to the frequency of the external clock signal that clocks the integrated circuit. As a result of the comparison, if the frequency of the input clock signal is greater than the frequency reference then operation of the integrated circuit is disrupted.
摘要翻译： 用于集成电路的调速器，其防止集成电路在选定频率之上的操作。 调速器产生频率参考，并将频率参考值与对集成电路进行时钟的外部时钟信号的频率进行比较。 作为比较的结果，如果输入时钟信号的频率大于频率参考值，则集成电路的操作被中断。
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公开(公告)号：US07404099B2
公开(公告)日：2008-07-22
申请号：US10918301
申请日：2004-08-13
CPC分类号： H03L7/0891 , H03L7/10
摘要： According to embodiments of the present invention, a phase-locked loop (PLL) may include circuitry to select a wide pulse width for the phase-frequency detector control signal when the PLL is in a frequency acquisition stage, a narrow pulse width for the phase-frequency detector control signal when the PLL is in a phase capture stage, and a wide pulse width of the phase-frequency detector control signal when the PLL is in a lock stage.
摘要翻译： 根据本发明的实施例，锁相环（PLL）可以包括当PLL处于频率采集级时为相位 - 频率检测器控制信号选择宽脉冲宽度的电路，用于相位的窄脉冲宽度 当PLL处于锁相阶段时，PLL处于相位捕获级中的频率检测器控制信号，以及相位 - 频率检测器控制信号的宽脉冲宽度。
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公开(公告)号：US07024324B2
公开(公告)日：2006-04-04
申请号：US10856907
申请日：2004-05-27
申请人： Michael C. Rifani , Keng L. Wong , Christopher Pan
发明人： Michael C. Rifani , Keng L. Wong , Christopher Pan
IPC分类号： G06F19/00
CPC分类号： G01R29/0273
摘要： A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.
摘要翻译： 本文描述了用于校准延迟元件的方法。 在一些实施例中，该方法可以包括用时钟沿生成时钟信号，使用可调延迟线产生具有参考边沿的参考信号以延迟时钟信号，以及延迟选定的一个时钟信号和参考信号通过 具有阵列延迟的阵列延迟元件的阵列延迟线。 在一些实施例中，该方法还可以包括调整可调延迟线以获得第一可调延迟，使得时钟和参考边沿在阵列延迟元件的一侧对准，调节可调延迟线以获得第二可调延迟 时钟和参考边沿在阵列延迟元件的另一侧对准，并且确定第一和第二可调延迟之间的延迟差以确定由阵列延迟元件提供的阵列延迟的值。 本发明的其它实施例可以包括但不限于适于促进实施上述方法的装置和系统。
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公开(公告)号：US06985041B2
公开(公告)日：2006-01-10
申请号：US10136390
申请日：2002-05-02
申请人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
发明人： Keng L. Wong , Niraj Bindal , Hong-Piao Ma , George Geannopoulos , Greg F. Taylor , Edward A. Burton
IPC分类号： H03B27/00
CPC分类号： G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/15013
摘要： A clock generating circuit is provided that includes a multiplexing device coupled to a clock distribution network to select between a synchronous mode and an asynchronous mode. The device may also include a plurality of distributed ring oscillators to drive the clock distribution network in the asynchronous mode. In the synchronous mode, the multiplexing device may pass a signal from a phase lock loop circuit located external to a core.
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公开(公告)号：US06531974B1
公开(公告)日：2003-03-11
申请号：US09545235
申请日：2000-04-07
申请人： Kent R. Callahan , Keng L. Wong
发明人： Kent R. Callahan , Keng L. Wong
IPC分类号： H03M166
CPC分类号： H03L7/0805 , H03K5/131 , H03K5/133 , H03K2005/00065 , H03K2005/00104 , H03K2005/00208 , H03L7/0995
摘要： Controlling time delay includes using a delay line and a digital to analog converter configured to provide a signal to the delay line and including digital inputs configured to control the delay through the delay line by controlling amplifier gain elements included in the digital to analog converter.
摘要翻译： 控制时间延迟包括使用延迟线和数模转换器，其被配置为向延迟线提供信号，并且包括被配置为通过控制包括在数模转换器中的放大器增益元件来控制延迟线的延迟的数字输入。
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公开(公告)号：US5801561A
公开(公告)日：1998-09-01
申请号：US842501
申请日：1997-04-21
IPC分类号： H03K17/22
CPC分类号： H03K17/22
摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.
摘要翻译： 一种减少上电期间集成电路竞争的方法和装置。 根据本发明的一个方面，在集成电路中包括初始化电路。 响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。 替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。 响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。
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公开(公告)号：US5696953A
公开(公告)日：1997-12-09
申请号：US597363
申请日：1996-02-08
CPC分类号： G06F1/3237 , G06F1/10 , G06F1/3203 , G06F1/3287 , Y02B60/1221 , Y02B60/1282
摘要： A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.
摘要翻译： 用于集成电路设备的时钟分配系统和时钟中断系统。 忽略与匹配级相关的效应，本发明包括时钟分配和中断系统，用于向集成电路器件的各种部件提供小于100皮秒的偏移的时钟信号。 本发明利用几级驱动器均匀地提供分布式时钟信号，每级具有RC匹配输入线。 本发明有利地位于位于微处理器拓扑周边的集成电路的电源环内的匹配级和时钟驱动器。 这样做是为了更好地预测这些线路周围的拓扑，以匹配这些线路的电容。 此外，该金属层提供较大的宽度尺寸线（因为顶层可以较厚），每单位面积具有较小的电阻，并且还通常避免与其它IC组件和电路的空间竞争。 本发明另外提供了利用功率管理单元选择性地降低集成设备内的各种组件并使能作为时钟分配系统的组件被包括的网络的能力。
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8.发明授权Multi-loop circuit capable of providing a delayed clock in phase locked loops 失效能够在锁相环中提供延迟时钟的多回路电路公开(公告)号：US07184503B2
公开(公告)日：2007-02-27
申请号：US11303682
申请日：2005-12-15
申请人： Keng L. Wong , Chee How Lim
发明人： Keng L. Wong , Chee How Lim
CPC分类号： H03L7/0891 , H03L7/095
摘要： A multi-loop circuit includes a first switching device to receive a first clock pulse and a second delayed pulse and produce a first output pulse including either the first clock pulse or the second delayed pulse. A first delay device receives the first output pulse and produces a first delayed pulse. A second switching device receives a second clock pulse and the first delayed pulse and produces a second output pulse including either the second clock pulse or the first delayed pulse. A second delay device receives the second output pulse and produces the second delayed pulse. A third switching device receives the first and second delayed pulses and produces a first output signal. A fourth switching device receives the first and second delayed pulses and produces a second output signal. A controller is coupled to control the first, second, third, and fourth switching devices.
摘要翻译： 多回路电路包括用于接收第一时钟脉冲和第二延迟脉冲并产生包括第一时钟脉冲或第二延迟脉冲的第一输出脉冲的第一开关器件。 第一延迟装置接收第一输出脉冲并产生第一延迟脉冲。 第二开关装置接收第二时钟脉冲和第一延迟脉冲，并产生包括第二时钟脉冲或第一延迟脉冲的第二输出脉冲。 第二延迟装置接收第二输出脉冲并产生第二延迟脉冲。 第三开关装置接收第一和第二延迟脉冲并产生第一输出信号。 第四开关装置接收第一和第二延迟脉冲并产生第二输出信号。 控制器被耦合以控制第一，第二，第三和第四开关装置。
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公开(公告)号：US06876717B1
公开(公告)日：2005-04-05
申请号：US10922193
申请日：2004-08-19
申请人： Feng Wang , Keng L. Wong
发明人： Feng Wang , Keng L. Wong
CPC分类号： H03L7/183 , H03K23/542 , H03K23/66
摘要： A counter has selectable divide factors using multiple multiplexers. The counter includes an inverter and cascading delay stages having selectable stage delays. The inverter connects a stage output of a last one of the delay stages to a stage input of a first one of the delay stages. Each delay stages includes a stage input to receive a quotient signal, at least two paths having different associated path delays each coupled to receive the quotient signal from the stage from the stage input, and a multiplexer. The multiplexer is coupled to selectively communicate the quotient signal from one of the at least two paths to a stage output to select one of the stage delays.
摘要翻译： 计数器具有使用多路复用器的可选分频因子。 该计数器包括具有可选阶段延迟的反相器和级联延迟级。 逆变器将最后一个延迟级的级输出连接到第一级延迟级的级输入。 每个延迟级包括用于接收商信号的级输入，具有不同相关联的路径延迟的至少两个路径，每个路径被耦合以从级输入端接收商信号，以及多路复用器。 多路复用器被耦合以选择性地将商信号从至少两条路径中的一条路径传送到级输出端，以选择一个级延迟。
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公开(公告)号：US06842056B1
公开(公告)日：2005-01-11
申请号：US10603722
申请日：2003-06-24
申请人： Keng L. Wong , Cangsang Zhao , Chee How Lim
发明人： Keng L. Wong , Cangsang Zhao , Chee How Lim
CPC分类号： G06F1/04 , H03L7/0891 , H03L7/23
摘要： A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.
摘要翻译： 使用级联锁相环（PLL）电路产生时钟频率的方法和装置包括分别耦合到第二PLL电路以产生微处理器I / O数据时钟信号和微处理器核心时钟信号的第一PLL电路。 在一个实施例中，第一PLL基于第一参考信号和第一反馈信号产生数据时钟信号，其中从数据时钟信号导出第一反馈信号。 此外，第二PLL电路至少部分地基于第二参考信号和第二反馈信号产生核心时钟信号，其中第二参考信号从数据时钟信号导出，并且第二反馈信号从核心时钟导出 信号。
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