Manufacture of semiconductor device having STI and semiconductor device manufactured
    1.
    发明授权
    Manufacture of semiconductor device having STI and semiconductor device manufactured 有权
    制造具有STI和半导体器件的半导体器件的制造

    公开(公告)号:US07037803B2

    公开(公告)日:2006-05-02

    申请号:US10721870

    申请日:2003-11-26

    IPC分类号: H01L21/76

    摘要: A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

    摘要翻译: 半导体器件制造方法具有以下步骤:(a)在半导体衬底上形成抛光阻挡层; (b)蚀刻半导体衬底以形成沟槽; (c)在所述沟槽的表面上形成氧化硅的第一衬垫绝缘层; (d)在所述第一衬垫绝缘层上形成氮化硅的第二衬垫绝缘层,所述第二衬垫绝缘层的厚度为至少20nm或至多8nm; (e1)在第一偏压下通过等离子体CVD沉积第二衬里绝缘层上的第三衬垫绝缘层氧化硅; 和(e2)以高于第一偏压的第二偏压通过等离子体CVD沉积氧化硅隔离层,隔离层埋设由第三衬里绝缘层限定的凹部。

    Semiconductor device with shallow trench isolation and its manufacture method
    2.
    发明授权
    Semiconductor device with shallow trench isolation and its manufacture method 失效
    具有浅沟槽隔离的半导体器件及其制造方法

    公开(公告)号:US07626234B2

    公开(公告)日:2009-12-01

    申请号:US11429962

    申请日:2006-05-09

    IPC分类号: H01L29/76

    摘要: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.

    摘要翻译: 半导体器件制造方法包括以下步骤:(a)在半导体衬底的表面上形成用于化学机械抛光的阻挡层; (b)在所述阻挡层和半导体衬底中形成元件隔离沟槽; (c)沉积覆盖所述沟槽的内表面的氮化物膜; (d)通过高密度等离子体CVD沉积第一氧化物膜,第一氧化膜埋入沉积有氮化物膜的沟槽的至少下部; (e)通过稀氢氟酸在沟槽的侧壁上洗出第一氧化膜; (f)通过高密度等离子体CVD沉积第二氧化膜,第二氧化膜在洗出之后埋入沟槽; 和(g)通过化学机械抛光去除阻挡层上的氧化物膜。

    Method for fabricating a semiconductor device
    5.
    发明申请
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号:US20050227476A1

    公开(公告)日:2005-10-13

    申请号:US11066570

    申请日:2005-02-28

    申请人: Kengo Inoue

    发明人: Kengo Inoue

    摘要: A semiconductor device has a multi-layer interconnection structure with a first interlayer insulation film and a second interlayer insulation film that is formed on the first interlayer insulation film and has a hardness and an elastic modulus larger than those of the first interlayer insulation film, and is fabricated by a step of forming a resist film on the second interlayer insulation film via an antireflective film, a step of exposing to light and developing the resist film to form a resist pattern, and a step of patterning the antireflective film and the multi-layer interconnection structure using the resist pattern as a mask, wherein a film with no stress or for storing compressive stress is used as the antireflective film.

    摘要翻译: 半导体器件具有多层互连结构,具有第一层间绝缘膜和第二层间绝缘膜,所述第一层间绝缘膜形成在第一层间绝缘膜上,并且具有比第一层间绝缘膜大的硬度和弹性模量,以及 通过在第二层间绝缘膜上经由防反射膜形成抗蚀剂膜的步骤,暴露于光并显影抗蚀剂膜以形成抗蚀剂图案的步骤,以及将抗反射膜和多反射膜图案化的步骤, 使用抗蚀剂图案作为掩模的层间互连结构,其中使用没有应力的膜或用于存储压缩应力的膜作为抗反射膜。

    NUMERICAL STRUCTURE-ANALYSIS CALCULATION SYSTEM
    6.
    发明申请
    NUMERICAL STRUCTURE-ANALYSIS CALCULATION SYSTEM 失效
    数值结构分析计算系统

    公开(公告)号:US20100100361A1

    公开(公告)日:2010-04-22

    申请号:US12528792

    申请日:2008-02-04

    IPC分类号: G06F17/50 G06F17/16

    CPC分类号: G06F17/5018 Y02T10/82

    摘要: The object is to enable the calculation of load transfer paths in case of distributed load applied to the structure with the numerical structure-analysis calculation system. The value of the parameter U** at each point is calculated according to the ratio of the complementary strain energy U at the application of load without fixing the point in the structure and the complementary strain energy U′ at the application of load with fixing one point in the structure. In the actual calculation, according to the complementary strain energy U, and the flexibility matrix CAC with respect to the loading point A and one point C in the structure, and the inverse matrix CCC−1 of the flexibility matrix with respect to point C, and the load pA at the loading point A, the value of the parameter U** (CACCCC−1CCApA·pA/(2U))at point C is calculated. Or, from the complementary strain energy U, and the inverse matrix CCC−1, and the displacement dC at point C, the value of the parameter U**(dC·CCC−1dC/(2U)) at point C is calculated.

    摘要翻译: 目的是使用数值结构分析计算系统在分布式负载施加到结构的情况下计算负载传输路径。 每个点处的参数U **的值根据在施加负载时的互补应变能U的比例而不固定结构中的点和在施加负载时的互补应变能U' 指向结构。 在实际计算中,根据互补应变能U,以及相对于装载点A和结构中的一个点C的柔性矩阵CAC以及相对于点C的柔性矩阵的逆矩阵CCC-1, 在加载点A处的负载pA,计算点C处的参数U **(CACCCC-1CCApA·pA /(2U))的值。 或者,从互补应变能U和逆矩阵CCC-1以及C点的位移dC,计算点C处的参数U **(dC·CCC-1dC /(2U))的值。

    Semiconductor device with shallow trench isolation and its manufacture method

    公开(公告)号:US20060255426A1

    公开(公告)日:2006-11-16

    申请号:US11429962

    申请日:2006-05-09

    IPC分类号: H01L29/00

    摘要: A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; (c) depositing a nitride film covering an inner surface of the trench; (d) depositing a first oxide film through high density plasma CVD, the first oxide film burying at least a lower portion of the trench deposited with the nitride film; (e) washing out the first oxide film on a side wall of the trench by dilute hydrofluoric acid; (f) depositing a second oxide film by high density plasma CVD, the second oxide film burying the trench after the washing-out; and (g) removing the oxide films on the stopper layer by chemical mechanical polishing.

    Numerical structure-analysis calculation system
    9.
    发明授权
    Numerical structure-analysis calculation system 失效
    数值结构分析计算系统

    公开(公告)号:US08352219B2

    公开(公告)日:2013-01-08

    申请号:US12528792

    申请日:2008-02-04

    CPC分类号: G06F17/5018 Y02T10/82

    摘要: The object is to enable the calculation of load transfer paths in case of distributed load applied to the structure with the numerical structure-analysis calculation system. The value of the parameter U** at each point is calculated according to the ratio of the complementary strain energy U at the application of load without fixing the point in the structure and the complementary strain energy U′ at the application of load with fixing one point in the structure. In the actual calculation, according to the complementary strain energy U, and the flexibility matrix CAC with respect to the loading point A and one point C in the structure, and the inverse matrix CCC−1 of the flexibility matrix with respect to point C, and the load pA at the loading point A, the value of the parameter U** (CACCCC−1CCApA·pA/(2U)) at point C is calculated. Or, from the complementary strain energy U, and the inverse matrix CCC−1, and the displacement dC at point C, the value of the parameter U**(dC·CCC−1dC/(2U)) at point C is calculated.

    摘要翻译: 目的是使用数值结构分析计算系统在分布式负载施加到结构的情况下计算负载传输路径。 每个点处的参数U **的值根据在施加负载时的互补应变能U的比例而不固定结构中的点和在施加负载时的互补应变能U' 指向结构。 在实际计算中,根据互补应变能U,以及相对于装载点A和结构中的一个点C的柔性矩阵CAC以及相对于点C的柔性矩阵的逆矩阵CCC-1, 在加载点A处的负载pA,计算点C处的参数U **(CACCCC-1CCApA·pA /(2U))的值。 或者,从互补应变能U和逆矩阵CCC-1以及C点的位移dC,计算点C处的参数U **(dC·CCC-1dC /(2U))的值。