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    Input line interface device and packet communication device
    1.
    发明授权
    Input line interface device and packet communication device 有权
    输入线路接口设备和分组通信设备

    公开(公告)号：US07366165B2

    公开(公告)日：2008-04-29

    申请号：US10079082

    申请日：2002-02-19

    申请人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

    发明人： Kenichi Kawarai ,  Masakatsu Nagata ,  Hiroshi Tomonaga ,  Naoki Matsuoka ,  Tsuguo Kato

    IPC分类号： H04Q11/00

    CPC分类号： H04L49/9094 ,  H04L12/46 ,  H04L45/60 ,  H04L47/2441 ,  H04L49/30 ,  H04L49/90

    摘要： An input line interface device that is used to accommodate packets from a high-speed line efficiently and to reduce a processing load on a back stage caused by routing control. A packet allotting section divides a variable-length packet, allots divided packets to parallel lines, and outputs the packets. A flow group classifying section classifies the packets into flow groups on each of the parallel lines. A sequence number giving section gives the packets sequence numbers corresponding to or independent of the flow groups. A buffering section stores the packets to which the sequence numbers have been given in a buffer or reads out them from the buffer to exercise sequence control over the packets in the flow groups. A flow separating switch separates the packets according to the flow groups and outputs the packets.

    摘要翻译： 一种输入线接口装置，用于有效地适应来自高速线路的分组，并减少由路由控制引起的后台处理负担。 分组分配部分分割可变长度分组，将分组分配给并行，并输出分组。 流组分类部分将每个并行线路上的分组分组为流组。 序列号给出部分给出与流组相对应或独立于流组的分组序列号。 缓冲部分将缓冲器中已经给出序列号的分组存储在缓冲器中，或者从缓冲器中读出它们以对流组中的分组进行序列控制。 流分离交换机根据流组分离报文，并输出报文。

    Scheduling control system and switch
    3.
    发明授权
    Scheduling control system and switch 失效
    调度控制系统和开关

    公开(公告)号：US07046685B1

    公开(公告)日：2006-05-16

    申请号：US09460898

    申请日：1999-12-14

    申请人： Naoki Matsuoka ,  Kenichi Kawarai ,  Hiroshi Tomonaga ,  Tsuguo Kato

    发明人： Naoki Matsuoka ,  Kenichi Kawarai ,  Hiroshi Tomonaga ,  Tsuguo Kato

    IPC分类号： H04L12/56 ,  H04L12/54 ,  H04L12/43 ,  H04J7/00

    CPC分类号： H04L49/1553 ,  H04L12/5601 ,  H04L41/0896 ,  H04L47/50 ,  H04L47/6225 ,  H04L49/3045 ,  H04L2012/5679 ,  H04L2012/5681

    摘要： A scheduling system is capable of causing no deterioration of characteristics even under equal and unequal loads, eliminating the necessity for high-speed repetitive scheduling and complicated arithmetic processes, simplifying its architecture and having its processing speed which does not depend upon a device capability. For attaining this system, an inter-highway pointer is updated to an adjacent line (rightward) when the scheduling for all the lines are finished. If the inter-highway pointer is updated N-times in the same direction (clockwise), the same pointer is updated to an adjacent line in a reverse direction (counterclockwise) in next N-processes of scheduling.

    摘要翻译： 调度系统即使在相等和不相等的负载下也不会导致特性恶化，消除了高速重复调度和复杂运算过程的必要性，简化了其架构并且具有不依赖于设备能力的处理速度。 为了实现该系统，当所有行的调度完成时，将将公路间指针更新为相邻行（向右）。 如果公路间指针以相同方向（顺时针）N次更新，则在下一个N个调度处理中，相同的指针在相反方向（逆时针）更新为相邻的行。

    Packet Switch
    5.
    发明授权
    Packet Switch 失效
    分组交换机

    公开(公告)号：US06963577B1

    公开(公告)日：2005-11-08

    申请号：US09643566

    申请日：2000-08-22

    申请人： Hiroshi Tomonaga ,  Naoki Matuoka ,  Kenichi Kawarai ,  Tsuguo Kato

    发明人： Hiroshi Tomonaga ,  Naoki Matuoka ,  Kenichi Kawarai ,  Tsuguo Kato

    IPC分类号： H04L12/18 ,  H04L12/28 ,  H04L12/775 ,  H04L12/863 ,  H04L12/879 ,  H04L12/933 ,  H04L12/937 ,  H04L12/945

    CPC分类号： H04L47/24 ,  H04L12/5601 ,  H04L49/106 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5679 ,  H04L2012/5681 ,  H04L2012/5683

    摘要： A packet switch includes an input buffer memory unit having a logic queue corresponding to an output line, a control module for a first pointer indicating a scheduling start input line, a control module for a second pointer indicating a scheduling start output line of scheduling target outlines, a request management control module for retaining transmission request data about a desired output line, a scheduling processing module for starting a retrieval from within plural pieces of transmission request data from the output line indicated by the second pointer, and selecting an output line that is not ensured by other input lines, a packet buffer memory unit for temporarily storing a plurality of fixed-length packets and sequentially outputting the fixed-length packets, a switch unit for switching the fixed-length packets outputted from the packet buffer memory unit, and an address management unit for segmenting an address of the packet buffer memory unit into fixed-length blocks for a plurality of packets, and managing the address on a block basis. With this construction, the memory address is managed on the block basis, and a memory capacity can be reduced by giving an intra-block individual address per queue when in writing or reading.

    摘要翻译： 分组交换机包括具有对应于输出线的逻辑队列的输入缓冲存储器单元，用于指示调度开始输入线的第一指针的控制模块，用于指示调度目标轮廓的调度开始输出行的第二指针的控制模块 ，用于保存关于期望输出线的发送请求数据的请求管理控制模块，用于从由第二指示器指示的输出线从多条发送请求数据中开始检索的调度处理模块，以及选择输出线 由其他输入线路不能保证，用于暂时存储多个固定长度分组并顺序地输出固定长度分组的分组缓冲存储器单元，用于切换从分组缓冲存储器单元输出的固定长度分组的切换单元，以及 地址管理单元，用于将分组缓冲存储器单元的地址分段成为a的固定长度块 多个分组，并且以块为基础管理地址。 利用这种结构，以块为基础管理存储器地址，并且可以通过在写入或读取时给出每个队列的块内单独地址来减小存储器容量。

    Router and mobile communication terminal for mobile communication network
    7.
    发明授权
    Router and mobile communication terminal for mobile communication network 有权
    路由器和移动通信终端用于移动通信网络

    公开(公告)号：US07277708B2

    公开(公告)日：2007-10-02

    申请号：US10125806

    申请日：2002-04-19

    申请人： Keiichi Nakatsugawa ,  Tsuguo Kato

    发明人： Keiichi Nakatsugawa ,  Tsuguo Kato

    IPC分类号： H04Q7/20

    CPC分类号： H04W36/0011 ,  H04L45/00 ,  H04L69/16 ,  H04W48/08 ,  H04W80/04 ,  H04W88/005 ,  H04W88/14

    摘要： The present invention provides a mobile communication network system comprising a first mobile communication network having a plurality of routers, a second mobile communication network having a plurality of routers, and a mobile communication terminal. A router located in an end section of a communication area of the first mobile communication network sends an end message indicating that it is located in the end section, to the mobile communication terminal. The terminal initiates communications with a router of the second mobile communication network, whilst the terminal is communicating with the router located in the end section, upon receiving the end message sent by the router located in the end section.

    摘要翻译： 本发明提供了一种移动通信网络系统，包括具有多个路由器的第一移动通信网络，具有多个路由器的第二移动通信网络和移动通信终端。 位于第一移动通信网络的通信区域的端部的路由器将表示其位于终端部分的结束消息发送到移动通信终端。 终端在接收到位于终端部分的路由器发送的结束消息时，终端与位于终端部分的路由器通信，终端与第二移动通信网络的路由器进行通信。

    Method of manufacturing a molding using a filler or an additive concentrated on an arbitrary portion or distributed at a gradient concentration
    8.
    发明授权
    Method of manufacturing a molding using a filler or an additive concentrated on an arbitrary portion or distributed at a gradient concentration 失效
    使用浓缩在任意部分上或以梯度浓度分布的填料或添加剂制造模塑品的方法

    公开(公告)号：US5589129A

    公开(公告)日：1996-12-31

    申请号：US491687

    申请日：1995-06-19

    申请人： Tsuguo Kato ,  Cao M. Thai

    发明人： Tsuguo Kato ,  Cao M. Thai

    IPC分类号： B29C70/62 ,  B29C70/68 ,  B29C35/08

    CPC分类号： B29C70/681 ,  B29C70/62 ,  B29K2105/002 ,  B29L2031/3406 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265

    摘要： A liquid resin composition prepared by mixing an ionic material and/or a chargeable material into a thermosetting or thermoplastic resin is injected into a mold having a predetermined inner shape, and a DC voltage is applied to the liquid resin composition to concentrate the ionic material and/or chargeable material on a desired portion or to distribute the ionic material and/or chargeable material continuously. Thereafter, the resin composition is thermally cured when the resin composition contains the thermosetting resin, or the resin composition is hardened by cooling when the resin composition contains the thermoplastic resin, thereby obtaining a molding having a predetermined shape.

    摘要翻译： 将通过将离子物质和/或可带电材料混合到热固性或热塑性树脂中制备的液体树脂组合物注入具有预定内部形状的模具中，并且将DC电压施加到液体树脂组合物上以浓缩离子材料和 /或所需部分上的可充电材料或连续分布离子材料和/或带电材料。 此后，当树脂组合物含有热固性树脂时，树脂组合物被热固化，或者当树脂组合物含有热塑性树脂时树脂组合物通过冷却硬化，从而获得具有预定形状的模制品。

    Information collection device and method for use with communications networks
    9.
    发明授权
    Information collection device and method for use with communications networks 失效
    用于通信网络的信息采集装置和方法

    公开(公告)号：US6005844A

    公开(公告)日：1999-12-21

    申请号：US978020

    申请日：1997-11-25

    申请人： Hideaki Ono ,  Ryuichi Takechi ,  Tsuguo Kato ,  Yutaka Ezaki ,  Mitsuharu Amano

    发明人： Hideaki Ono ,  Ryuichi Takechi ,  Tsuguo Kato ,  Yutaka Ezaki ,  Mitsuharu Amano

    IPC分类号： H04L12/56 ,  H04Q11/04 ,  H04L12/14

    CPC分类号： H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5684

    摘要： A storage unit includes an alarm state/timer table, an alarm state table, an alarm state OR-representation table, an alarm state change OR-representation table, an alarm state latch circuit, and a statistical information memory. A collection unit extracts the identifier and data from a cell that passes through a switching unit. An update unit updates associated data in the storage unit. A readout unit reads the updated data and sends it to a call processing processor. An address generation section selectively generates the address for data needing to be updated. An adjustment section forces the readout unit to wait until a cell slot arrives in which no data is updated.

    摘要翻译： 存储单元包括报警状态/定时器表，报警状态表，报警状态或表示表，报警状态改变OR表示表，报警状态锁存电路和统计信息存储器。 收集单元从通过切换单元的单元提取标识符和数据。 更新单元更新存储单元中的相关数据。 读出单元读取更新的数据并将其发送到呼叫处理处理器。 地址生成部选择性地生成需要更新的数据的地址。 调整部分强制读出单元等待，直到小区时隙到达，而没有更新数据。

    Phase adjustment circuit
    10.
    发明授权
    Phase adjustment circuit 失效
    相位调整电路

    公开(公告)号：US5051990A

    公开(公告)日：1991-09-24

    申请号：US468284

    申请日：1990-01-22

    申请人： Tsuguo Kato

    发明人： Tsuguo Kato

    IPC分类号： H04L7/00 ,  H04J3/06 ,  H04L7/033

    CPC分类号： H04J3/0602 ,  H04J3/0688

    摘要： A phase adjustment circuit uses a broad band circuit for processing a plurality of high speed highway data comprising m bit frames. The phase adjustment circuit provides a master frame pulse based on a frame pulse selected from respective frame pulses in the high speed highway and delayed in phase by the maximum amount and provides a master clock based on a high speed highway clock corresponding to the master frame pulse. The phase adjustment circuit receives a plurality of high speed highway data by using the master clock and the master frame pulse.