公开(公告)号：US07843210B2

公开(公告)日：2010-11-30

申请号：US12656696

申请日：2010-02-12

申请人： Kenji Ijitsu

发明人： Kenji Ijitsu

IPC分类号： H03K19/00 ,  G01R31/28

CPC分类号： G01R31/31707 ,  G01R31/318544

摘要： A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit.

摘要翻译： 所公开的半导体集成电路器件包括逻辑电路，逻辑电路写入数据并由逻辑电路读出数据的存储器电路，当逻辑电路将数据写入到存储器电路时， 选择电路，选择从寄存器电路输出的数据和从存储器电路输出的数据，并将选择的数据输出到逻辑电路。 此外，在半导体集成电路装置中，在逻辑电路的动作试验中，选择电路选择从寄存器电路输出的数据，并将选择的数据输出到逻辑电路。

公开(公告)号：US07446589B2

公开(公告)日：2008-11-04

申请号：US11319729

申请日：2005-12-29

申请人： Kenji Ijitsu

发明人： Kenji Ijitsu

IPC分类号： G05F1/04 ,  H03K3/00

CPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/10 ,  H03K5/06 ,  H03K2005/00293

摘要： Pulse generation circuit has a P-MOS transistor having a drain electrode connected to a first power source; a first N-MOS transistor having a drain electrode connected to the source electrode of the P-MOS transistor; a second N-MOS transistor having a drain electrode connected to the source electrode of the first N-MOS transistor, a gate electrode receiving an input pulse signal, and a source electrode connected to the second power source; a delay circuit having an input terminal connected to the source electrode of the P-MOS transistor and the drain electrode of the first N-MOS transistor and an output terminal connected to gate electrode of the P-MOS transistor and gate electrode of the first N-MOS transistor; an inverter input connected to the source electrode of the P-MOS transistor and the drain electrode of the second N-MOS transistor for outputting a generated pulse; and a keeper keeping voltage level to the inverter.

摘要翻译： 脉冲发生电路具有连接到第一电源的漏电极的P-MOS晶体管; 第一N-MOS晶体管，其漏极连接到P-MOS晶体管的源电极; 第二N-MOS晶体管，具有连接到第一N-MOS晶体管的源电极的漏电极，接收输入脉冲信号的栅极电极和连接到第二电源的源电极; 具有连接到P-MOS晶体管的源电极和第一N-MOS晶体管的漏极的输入端的延迟电路和连接到P-MOS晶体管的栅电极和与第一N-MOS晶体管的栅电极连接的输出端 -MOS晶体管; 连接到P-MOS晶体管的源电极和第二N-MOS晶体管的漏电极的反相器输入端，用于输出产生的脉冲; 并保持对变频器的电压水平。

公开(公告)号：US20100148816A1

公开(公告)日：2010-06-17

申请号：US12656696

申请日：2010-02-12

申请人： Kenji Ijitsu

发明人： Kenji Ijitsu

IPC分类号： H03K19/00 ,  H03K19/173

CPC分类号： G01R31/31707 ,  G01R31/318544

摘要： A disclosed semiconductor integrated circuit device includes a logic circuit, a memory circuit to which data are written by the logic circuit and from which the data are read by the logic circuit, a register circuit holding the data when the logic circuit writes the data to the memory circuit, and a selector circuit selecting one of data output from the register circuit and data output from the memory circuit, and outputting the selected data to the logic circuit. Further in the semiconductor integrated circuit device, in an operational test of the logic circuit, the selector circuit selects the data output from the register circuit and outputs the selected data to the logic circuit.

公开(公告)号：US5440696A

公开(公告)日：1995-08-08

申请号：US84451

申请日：1993-07-01

申请人： Kenji Ijitsu ,  Masanobu Yuhara ,  Hidenobu Ohta

发明人： Kenji Ijitsu ,  Masanobu Yuhara ,  Hidenobu Ohta

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F15/16 ,  G06F15/177 ,  G06F13/00

CPC分类号： G06F12/0848 ,  G06F12/0831

摘要： An internal address bus, which is connected between a bus control unit and a memory control unit, is formed by a bidirectional bus. The bidirectional internal address bus is connected to an external address transferring bus which is used to transfer a write address in a system bus to the memory control unit. The bidirectional internal address bus is commonly used for renewal and invalidation of first and second buffers for an instruction cache and operand cache. Therefore, in the present invention, the number of the internal bus lines can be reduced, a control constitution can be simplified, and a consistency of contents in a plurality of internal buffers and the main memory can be easily maintained.

摘要翻译： 连接在总线控制单元和存储器控制单元之间的内部地址总线由双向总线形成。 双向内部地址总线连接到用于将系统总线中的写入地址传送到存储器控制单元的外部地址传输总线。 双向内部地址总线通​​常用于指令高速缓存和操作数高速缓存的第一和第二缓冲器的更新和无效。 因此，在本发明中，能够减少内部总线的数量，能够简化控制结构，能够容易地维持多个内部缓冲器和主存储器内容的一致性。

公开(公告)号：US20090240900A1

公开(公告)日：2009-09-24

申请号：US12397672

申请日：2009-03-04

申请人： Yasuhide Sosogi ,  Kenji Ijitsu ,  Seiji Murata

发明人： Yasuhide Sosogi ,  Kenji Ijitsu ,  Seiji Murata

IPC分类号： G06F12/00

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  Y02D10/13

摘要： A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal.

摘要翻译： 存储器包括多个块，每个块包括连接到划分的位线的多个存储单元阵列，第一解码器，其基于输入的地址信号产生用于选择任何块的块选择信号;第一解码器， 相应的块，每个读/写部分执行属于其自己的块的存储单元阵列的读或写，并且信号生成部分各自生成用于使属于所选择的读/写部分的读/写部分的操作控制信号 当其块被块选择信号选择时，该块成为操作状态。 每个信号产生部分当其块未被块选择信号选择时，产生用于使属于其块的读/写部分处于非操作状态的操作控制信号。

公开(公告)号：US6118708A

公开(公告)日：2000-09-12

申请号：US208975

申请日：1998-12-11

申请人： Katsuya Yoshida ,  Tamiji Akita ,  Kenji Ijitsu

发明人： Katsuya Yoshida ,  Tamiji Akita ,  Kenji Ijitsu

IPC分类号： G11C11/41 ,  G11C7/18 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C7/18

摘要： The present invention concerns a memory structure wherein a plurality of memory cells such as SRAM are provided in columns and a plurality of bit line pairs are provided for each column. A write circuit drives a first bit line pair and writes data to the memory cells in the column; at the same time, a sense amp reads data by means of the second bit line pair. In that case, the first bit line pair and second bit line pair, provided in the same column, are driven with opposite phase signals. To prevent the reversal of the small potential difference of the second bit line pair for reading at that time, two bit lines, one bit line from the first and second bit line pairs, are arranged parallel in a first wiring layer and are interspersed with a fixed potential wiring. Furthermore, the two other bit lines from the first and second bit line pairs, are arranged parallel in a second wiring layer provided via an insulating layer and are interspersed with a fixed potential wiring. With such a structure, the first bit line pair and second bit line pair are disposed in each wiring layer and interposed in the fixed potential wiring; therefore, crosstalk therebetween is prevented even when the bit line pairs are driven with opposite phase signals and erroneous read operations are prevented.

摘要翻译： 本发明涉及一种存储器结构，其中诸如SRAM之类的多个存储器单元被提供在列中，并且为每列提供多个位线对。 写入电路驱动第一位线对并将数据写入列中的存储器单元; 同时，读出放大器通过第二位线对读取数据。 在这种情况下，在同一列中提供的第一位线对和第二位线对以相反相位信号驱动。 为了防止当时读取的第二位线对的小电位差的反转，来自第一和第二位线对的一个位线的两个位线平行布置在第一布线层中并且散布有 固定电位接线。 此外，来自第一位线对和第二位线对的另外两条位线平行布置在经由绝缘层提供的第二布线层中，并且散布有固定电位布线。 利用这种结构，第一位线对和第二位线对设置在每个布线层中并插入固定电位布线中; 因此，即使当位线对以相反的相位信号被驱动并且防止错误的读取操作时，也阻止它们之间的串扰。

公开(公告)号：US08000157B2

公开(公告)日：2011-08-16

申请号：US12198373

申请日：2008-08-26

申请人： Kenji Ijitsu

发明人： Kenji Ijitsu

IPC分类号： G11C7/00

CPC分类号： G11C29/14 ,  G11C11/41 ,  G11C29/12015

摘要： A timing generating circuit generates a control clock (1) and a test clock (2) based on an externally input clock CLK, and outputs the generated clocks to a testing circuit. The control clock (1) is a signal the phase of which is delayed by a predetermined amount with reference to the clock CLK. This predetermined amount can be set/changed with an external test signal. The test clock (2) is nearly an inversion signal of the clock CLK. The testing circuit generates various types of control signals (4) based on either of the clocks (1) and (2), and distributes the signals to a controlling circuit. Which of the clocks (1) and (2) is selected in the testing circuit can be set with an external test signal.

摘要翻译： 定时发生电路基于外部输入时钟CLK产生控制时钟（1）和测试时钟（2），并将产生的时钟输出到测试电路。 控制时钟（1）是相对于时钟CLK被延迟预定量的信号。 该预定量可以通过外部测试信号来设定/改变。 测试时钟（2）几乎是时钟CLK的反相信号。 测试电路基于时钟（1）和（2）中的任一个产生各种类型的控制信号（4），并将信号分配给控制电路。 在测试电路中选择哪个时钟（1）和（2）可以使用外部测试信号进行设置。

公开(公告)号：US20060097768A1

公开(公告)日：2006-05-11

申请号：US11319729

申请日：2005-12-29

申请人： Kenji Ijitsu

发明人： Kenji Ijitsu

IPC分类号： G06F1/04

CPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/10 ,  H03K5/06 ,  H03K2005/00293

摘要： There is provided a pulse generation circuit having a small input load and capable of self-reset. The pulse generation circuit includes: a P-MOS transistor having a drain electrode connected to a first power source line; a first N-MOS transistor having a drain electrode connected to the source electrode of the P-MOS transistor; a second N-MOS transistor having a drain electrode connected to the source electrode of the first N-MOS transistor, a gate electrode connected to the input line to which an input pulse signal is input, and a source electrode connected to the second power source line; a delay circuit having an input terminal connected to the source electrode of the P-MOS transistor and the drain electrode of the first N-MOS transistor and an output terminal connected to the gate electrode of the P-MOS transistor and the gate electrode of the first N-MOS transistor; an inverter having an input terminal connected to the source electrode of the P-MOS transistor and the drain electrode of the second N-MOS transistor and an output terminal connected to the output line for outputting a generated pulse; and a keeper for keeping the voltage level of the line connected to the input terminal of the inverter.

摘要翻译： 提供了具有小的输入负载并且能够自复位的脉冲发生电路。 脉冲发生电路包括：具有连接到第一电源线的漏电极的P-MOS晶体管; 第一N-MOS晶体管，其漏极连接到P-MOS晶体管的源电极; 第二N-MOS晶体管，具有连接到第一N-MOS晶体管的源电极的漏电极，连接到输入脉冲信号输入的输入线的栅电极和连接到第二电源的源电极 线; 具有连接到P-MOS晶体管的源电极和第一N-MOS晶体管的漏电极的输入端和与P-MOS晶体管的栅电极连接的输出端和 第一N-MOS晶体管; 反相器，具有连接到P-MOS晶体管的源电极和第二N-MOS晶体管的漏电极的输入端子和连接到输出线的输出端子，用于输出产生的脉冲; 以及用于保持连接到逆变器的输入端子的线路的电压电平的保持器。