公开(公告)号：US20090029524A1

公开(公告)日：2009-01-29

申请号：US12244621

申请日：2008-10-02

申请人： Kenji KANAMITSU ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji KANAMITSU ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

摘要翻译： 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

公开(公告)号：US06544839B1

公开(公告)日：2003-04-08

申请号：US09473297

申请日：1999-12-28

申请人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L218242

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

摘要翻译： 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

公开(公告)号：US07524729B2

公开(公告)日：2009-04-28

申请号：US11189833

申请日：2005-07-27

申请人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L21/76 ,  H01L21/336

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

摘要翻译： 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

公开(公告)号：US20050260820A1

公开(公告)日：2005-11-24

申请号：US11189833

申请日：2005-07-27

申请人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L27/06 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

摘要翻译： 一种半导体集成电路器件及其制造方法。 由元件隔离沟槽围绕的有源区的基板的表面在有源区的中心部分水平平坦，但是朝向有源区的肩部中的元件隔离沟的侧壁落下。 该倾斜面包含两个具有不同倾斜角的倾斜面。 有源区的中心部附近的第一倾斜面比较陡，元件隔离沟的侧壁附近的第二倾斜面比第一倾斜面更平缓。 有源区的肩部中的基板的表面完全是圆形的，并且没有角部。

公开(公告)号：US06967141B2

公开(公告)日：2005-11-22

申请号：US10919432

申请日：2004-08-17

申请人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L27/06 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

公开(公告)号：US20050014340A1

公开(公告)日：2005-01-20

申请号：US10919432

申请日：2004-08-17

申请人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

发明人： Kenji Kanamitsu ,  Kouzou Watanabe ,  Norio Suzuki ,  Norio Ishitsuka

IPC分类号： H01L27/06 ,  H01L21/28 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823878 ,  H01L21/28061 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/6659

摘要： A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

公开(公告)号：US06858515B2

公开(公告)日：2005-02-22

申请号：US10638485

申请日：2003-08-12

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device free from electric failure in transistors at upper trench edges can be produced by a simplified process comprising basic steps of forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation presention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film, etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; oxidizing the trench formed in the semiconductor substrate; embedding an embedding isolation film in the oxidized trench; removing the embedding isolation film formed on the oxidation prevention film; removing the oxidation prevention film formed on the circuit-forming side of the semiconductor substrate; and removing the pad oxide film formed on the circuit-forming side of the semiconductor substrate, where round upper trench edges with a curvature can be obtained, if necessary, by conducting isotropic etching of exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 在上沟槽边缘处的晶体管中没有电故障的半导体器件可以通过简化的工艺制造，包括在半导体衬底的电路形成侧形成衬垫氧化膜的基本步骤; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化呈现膜和衬垫氧化膜，从而暴露半导体衬底的表面; 水平地凹陷衬垫氧化膜，通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 氧化在半导体衬底中形成的沟槽; 在氧化沟槽中嵌入嵌入隔离膜; 去除形成在防氧化膜上的嵌入隔离膜; 去除形成在半导体衬底的电路形成侧的氧化防止膜; 以及去除形成在半导体衬底的电路形成侧的衬垫氧化膜，其中如果需要，可以获得具有曲率的圆形上沟槽边缘，通过对半导体衬底的暴露表面进行各向同性蚀刻并且使衬垫的水平凹陷 氧化膜在沟槽氧化之前，因此只需要一个氧化步骤。

公开(公告)号：US06635945B1

公开(公告)日：2003-10-21

申请号：US09580953

申请日：2000-05-30

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Kozo Watanabe ,  Kenji Kanamitsu

IPC分类号： H01L2900

CPC分类号： H01L21/76232 ,  H01L29/0657

摘要： A semiconductor device and process of forming the device are described. The process includes forming a pad oxide film on the circuit-forming side of a semiconductor substrate; forming an oxidation prevention film on the pad oxide film; removing the oxidation prevention film and the pad oxide film at a desired position, thereby exposing the surface of the semiconductor substrate; horizontally recessing the pad oxide film; etching the exposed surface of the semiconductor substrate by isotropic etching; forming a trench to a desired depth, using the oxidation prevention film as a mask; horizontally recessing the pad oxide film; and oxidizing the trench formed in the semiconductor substrate. The produced device has round upper trench edges obtained by conducting isotropic etching of the exposed surface of the semiconductor substrate and horizontally recessing of the pad oxide film before the oxidation of the trench, whereby only one oxidation step is required.

摘要翻译： 描述半导体器件和形成器件的工艺。 该工艺包括在半导体衬底的电路形成侧上形成衬垫氧化膜; 在衬垫氧化膜上形成氧化防止膜; 在期望的位置除去氧化防止膜和焊盘氧化膜，从而暴露半导体衬底的表面; 使衬垫氧化膜水平地凹陷; 通过各向同性蚀刻蚀刻半导体衬底的暴露表面; 使用氧化防止膜作为掩模，形成期望深度的沟槽; 使衬垫氧化膜水平地凹陷; 以及氧化在半导体衬底中形成的沟槽。 所制造的器件具有圆形的上沟槽边缘，其通过对半导体衬底的暴露表面进行各向同性蚀刻并在沟槽氧化之前水平凹陷焊盘氧化膜而获得，由此仅需要一个氧化步骤。

公开(公告)号：US20050196935A1

公开(公告)日：2005-09-08

申请号：US11108827

申请日：2005-04-19

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

公开(公告)号：US06881646B2

公开(公告)日：2005-04-19

申请号：US10392916

申请日：2003-03-21

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Norio Suzuki ,  Yasushi Matsuda ,  Yasuko Yoshida ,  Hirohiko Yamamoto ,  Masamichi Kobayashi ,  Akira Takamatsu ,  Hirofumi Shimizu ,  Kazushi Fukuda ,  Shinichi Horibe ,  Toshio Nozoe

IPC分类号： H01L21/31 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/76235 ,  H01L29/78

摘要： A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

摘要翻译： 一种制造半导体器件的方法，该半导体器件具有高度可靠的凹槽隔离结构，其具有在凹槽上边缘处形成的所需曲率半径，并且不形成任何步骤。 通过减小半导体衬底上的元件隔离槽的槽上边缘周围的应力产生，从而优化元件隔离槽的形状并使器件更精细并提高器件电气特性来制造器件。