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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE
    1.
    发明授权
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE 失效
    制造双门结构半导体器件的方法以及制造的半导体器件，其中包括形成具有较低电阻的N型和P型覆层的覆盖区域

    公开(公告)号：US06620666B2

    公开(公告)日：2003-09-16

    申请号：US09766844

    申请日：2001-01-23

    申请人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    发明人： Kenji Yoshiyama ,  Keiichi Higashitani ,  Masao Sugiyama

    IPC分类号： H01L21337

    CPC分类号： H01L21/823842

    摘要： There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

    摘要翻译： 描述了制造双栅极结构的半导体器件的方法，该方法防止在双栅极结构的栅电极中发生高电阻局部区域。 在隔离氧化膜上形成要成为双栅极结构的栅电极的导电层的多晶硅层。 将N型杂质注入到多晶硅膜的n型注入区域中，同时将光致抗蚀剂膜作为掩模。 将P型杂质注入多晶硅膜3的p型杂质区，同时将另一种光致抗蚀剂膜作为掩模。 进行n型杂质的注入和p型杂质的注入，使得不可避免地形成以这些重叠的方式掺杂这些杂质的重叠区域。

    Layout of well contacts and source contacts of a semiconductor device
    5.
    发明授权
    Layout of well contacts and source contacts of a semiconductor device 有权
    半导体器件的阱触点和源触点的布局

    公开(公告)号：US6064099A

    公开(公告)日：2000-05-16

    申请号：US285044

    申请日：1999-04-01

    申请人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

    发明人： Keiichi Yamada ,  Atsushi Maeda ,  Kenji Yoshiyama ,  Keiichi Higashitani

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/74 ,  H01L23/485 ,  H01L29/417 ,  H01L29/41

    CPC分类号： H01L29/66636 ,  H01L21/743 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41766 ,  H01L2924/0002

    摘要： There is described a semiconductor device intended to increase a degree of integration of transistor without impairing a desired element characteristic. An n-type source region and an n-type drain region are formed in a p-well which acts as a substrate region of an NMOS transistor. Further, there are formed a first contact plug to be electrically connected to the n-type source region and a second contact plug to be electrically connected to the n-type drain region. The n-type source region is provided so as to become short-circuited with the p-well. The n-type drain region is provided so as not to become short-circuited with the p-well. The n-type source region is formed so as to become smaller than the n-type drain region.

    摘要翻译： 描述了一种旨在增加晶体管集成度而不损害所需元件特性的半导体器件。 在作为NMOS晶体管的基板区域的p阱中形成n型源极区域和n型漏极区域。 此外，形成电连接到n型源极区域的第一接触插塞和与n型漏极区域电连接的第二接触插塞。 n型源极区域被设置为与p阱短路。 设置n型漏极区以不与p阱短路。 n型源极区域形成为小于n型漏极区域。

    Semiconductor device with self-aligned contact structure
    6.
    发明授权
    Semiconductor device with self-aligned contact structure 失效
    具有自对准接触结构的半导体器件

    公开(公告)号：US06479873B1

    公开(公告)日：2002-11-12

    申请号：US09444848

    申请日：1999-11-22

    申请人： Kenji Yoshiyama ,  Keiichi Higashitani

    发明人： Kenji Yoshiyama ,  Keiichi Higashitani

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/28518

    摘要： A semiconductor device more reduced in size and a manufacturing method thereof are provided. A gate electrode is covered with a silicon nitride film having a selecting ratio greater than an NSG film under a prescribed etching condition. A cobalt suicide film is formed on an upper surface of source/drain regions. Furthermore, a refractory metal silicide film forming the gate electrode is formed by a cobalt silicide film.

    摘要翻译： 提供了一种尺寸更小的半导体器件及其制造方法。 在规定的蚀刻条件下，用选择比大于NSG膜的氮化硅膜覆盖栅电极。 在源/漏区的上表面上形成硅化硅膜。 此外，通过硅化钴膜形成形成栅电极的难熔金属硅化物膜。

    Method for forming a semiconductor device having a plurality of circuits parts
    9.
    发明授权
    Method for forming a semiconductor device having a plurality of circuits parts 有权
    用于形成具有多个电路部分的半导体器件的方法

    公开(公告)号：US06468857B2

    公开(公告)日：2002-10-22

    申请号：US09927635

    申请日：2001-08-13

    申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

    发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

    IPC分类号： H01L218242

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

    摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

    摘要翻译： 提供一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管一起提供。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），能够防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。

    Semiconductor device, and method for manufacturing the same
    10.
    发明授权
    Semiconductor device, and method for manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06267479B1

    公开(公告)日：2001-07-31

    申请号：US09241138

    申请日：1999-02-02

    申请人： Keiichi Yamada ,  Hiroshi Kawashima ,  Keiichi Higashitani

    发明人： Keiichi Yamada ,  Hiroshi Kawashima ,  Keiichi Higashitani

    IPC分类号： H01L31119

    CPC分类号： H01L21/823807 ,  H01L21/823857 ,  H01L21/823892

    摘要： There is described a semiconductor device which includes in a single chip a high withstanding voltage transistor and a low withstanding voltage transistor and which imparts each of the transistors with a relevant threshold voltage and a characteristic suitable for retarding hot carriers. Specifically, an impurity profile is imparted to a lightly-doped extension (LDDEX) region formed across a channel region of a low withstanding voltage NMOS transistor, and a different impurity profile is imparted to an LDDEX region formed across a channel region of a high withstanding voltage NMOS transistor. These impurity profiles bring the threshold voltages of the MOS transistors to individual relevant voltages and retard hot carriers in the individual MOS transistors.

    摘要翻译： 描述了一种半导体器件，其在单个芯片中包括高耐压晶体管和低耐压晶体管，并且使每个晶体管具有适当的延迟热载流子的相关阈值电压和特性。 具体地说，杂质分布被赋予在低耐压NMOS晶体管的沟道区域上形成的轻掺杂延伸（LDDEX）区域，并且不同的杂质分布被赋予形成在高耐压的沟道区域上的LDDEX区域 电压NMOS晶体管。 这些杂质分布将MOS晶体管的阈值电压带到单独的相关电压并延迟各个MOS晶体管中的热载流子。