公开(公告)号：US20050062099A1

公开(公告)日：2005-03-24

申请号：US10981537

申请日：2004-11-05

申请人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

发明人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/792

CPC分类号： H01L29/6656 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823468

摘要： A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

摘要翻译： 提供一种半导体器件及其制造方法，其能够防止栅绝缘膜的质量恶化，从而防止器件的电特性劣化。 在包括多个场效应晶体管的半导体器件中，在一个栅电极19的一侧形成氧化保护膜21。

公开(公告)号：US06853030B2

公开(公告)日：2005-02-08

申请号：US10370762

申请日：2003-02-24

申请人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

发明人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/788 ,  H01L27/01 ,  H01L27/12 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6656 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823468

摘要： A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

摘要翻译： 提供一种半导体器件及其制造方法，其能够防止栅绝缘膜的质量恶化，从而防止器件的电特性劣化。 在包括多个场效应晶体管的半导体器件中，在一个栅电极19的一侧形成氧化保护膜21。

公开(公告)号：US06541823B1

公开(公告)日：2003-04-01

申请号：US09038020

申请日：1998-03-11

申请人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

发明人： Kenji Yoshiyama ,  Motoshige Igarashi ,  Keiichi Yamada ,  Katsuya Okada ,  Keiichi Higashitani

IPC分类号： H01L2701

CPC分类号： H01L29/6656 ,  H01L21/28247 ,  H01L21/823462 ,  H01L21/823468

摘要： A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

摘要翻译： 提供一种半导体器件及其制造方法，其能够防止栅绝缘膜的质量恶化，从而防止器件的电特性劣化。 在包括多个场效应晶体管的半导体器件中，在一个栅电极19的一侧形成有氧化保护膜21。

公开(公告)号：US6165878A

公开(公告)日：2000-12-26

申请号：US221128

申请日：1998-12-28

申请人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

发明人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/31 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/027 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

摘要翻译： 一种制造半导体器件的方法，如果接触孔从其正确的位置偏移，则可以防止栅电极和扩散层区域之间的短路。 在栅电极上形成具有对层间绝缘膜的蚀刻选择性的材料，以作为防止形成接触孔的盖。 不需要在暴露于接触孔的互连线上形成材料。

公开(公告)号：US6037630A

公开(公告)日：2000-03-14

申请号：US976076

申请日：1997-11-21

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/7833 ,  H01L29/7836 ,  H01L21/28035 ,  Y10S257/90

摘要： A first polysilicon film which contains phosphorus as an impurity is formed on a semiconductor substrate. A second polysilicon film which is higher in phosphorus concentration than the first polysilicon film is formed on the first polysilicon film. The second polysilicon film is anisotropically etched to expose a surface of the first polysilicon film. Thermal oxidation is then performed. A surface of the first polysilicon film and a surface of the second polysilicon film are oxidized according to their respective oxidization rates depending on their respective phosphorus concentrations. Thus, a semiconductor device in which the size of the gate electrode can be readily controlled and damage to the semiconductor substrate or the like can be suppressed, is obtained.

摘要翻译： 在半导体衬底上形成含有磷作为杂质的第一多晶硅膜。 在第一多晶硅膜上形成磷浓度高于第一多晶硅膜的第二多晶硅膜。 第二多晶硅膜被各向异性蚀刻以暴露第一多晶硅膜的表面。 然后进行热氧化。 第一多晶硅膜的表面和第二多晶硅膜的表面根据它们各自的氧化速率而被氧化，这取决于它们各自的磷浓度。 因此，可以抑制其中可以容易地控制栅电极的尺寸并损害半导体衬底等的半导体器件。

公开(公告)号：US06468857B2

公开(公告)日：2002-10-22

申请号：US09927635

申请日：2001-08-13

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L218242

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

摘要翻译： 提供一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管一起提供。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），能够防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。

公开(公告)号：US20050112832A1

公开(公告)日：2005-05-26

申请号：US10982903

申请日：2004-11-08

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/336 ,  H01L21/04 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L27/0629 ,  H01L28/20

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

公开(公告)号：US06841459B2

公开(公告)日：2005-01-11

申请号：US10288458

申请日：2002-11-06

申请人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

发明人： Hiroshi Kawashima ,  Motoshige Igarashi ,  Keiichi Higashitani

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/04 ,  H01L21/336

CPC分类号： H01L28/20 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/0629

摘要： A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

摘要翻译： 在将各种杂质植入到所述多晶硅膜中之后，在多晶硅膜中激活作为栅电极和电阻元件的各杂质的热处理被执行，所述多晶硅膜为栅电极，电阻元件涂覆有氧化物膜 多晶硅膜是栅电极和电阻元件。 这里，通过控制氧化膜的厚度来调节作为栅电极和电阻元件的多晶硅膜中各杂质的浓度。 从而调节杂质活化程度。

公开(公告)号：US06299314B1

公开(公告)日：2001-10-09

申请号：US09494785

申请日：2000-01-31

申请人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Motoshige Igarashi ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823443 ,  H01L21/823475

摘要： Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (3) of gate structures (GT11 to GT13) is covered with an upper nitride film (4) and sidewall nitride film (5). Therefore, when an interlayer insulating film (10) being oxide film is selectively removed for forming contact holes (CH1 and CH2), the upper nitride film (4) and sidewall nitride film (5) are not removed, thereby preventing the gate electrode (3) from being exposed. Particularly, in the gate structures (GT11 and GT12), even when the contact hole (CH1) is dislocated to either side, no short-circuit is developed between a conductor layer (CL1) and the gate electrode (3). Thus, the gate structures (GT11 and GT12) can be disposed without being restricted by the alignment margin of the contact hole (CH1), and the distance between the gates can be reduced for attaining high integration.

摘要翻译： 提供了一种半导体器件及其制造方法，其中将SAC结构的MOS晶体管和硅化物结构的MOS晶体管组合在一起。 栅极结构（GT11〜GT13）的栅极电极（3）被上部氮化膜（4）和侧壁氮化物膜（5）覆盖。 因此，为了形成接触孔（CH1，CH2）选择性地除去作为氧化膜的层间绝缘膜（10），不会去除上部氮化物膜（4）和侧壁氮化物膜（5），从而防止栅电极 3）不被暴露。 特别地，在栅极结构（GT11和GT12）中，即使接触孔（CH1）位于任一侧，也不会在导体层（CL1）和栅电极（3）之间产生短路。 因此，栅极结构（GT11和GT12）可以被布置而不受接触孔（CH1）的对准边缘的限制，并且可以减小栅极之间的距离以获得高集成度。

公开(公告)号：US08269284B2

公开(公告)日：2012-09-18

申请号：US13019600

申请日：2011-02-02

申请人： Koji Nil ,  Motoshige Igarashi

发明人： Koji Nil ,  Motoshige Igarashi

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L27/11 ,  H01L27/1104

摘要： There are provided a method of manufacturing a semiconductor device which achieves a reduction in implantation masks, and such a semiconductor device. By implanting boron into NMOS regions using a resist mask and another resist mask as the implantation masks, p-type impurity regions serving as the halo regions of access transistors and drive transistors are formed. By further implanting phosphorus or arsenic into a PMOS region using another resist mask as the implantation mask, n-type impurity regions serving as the halo regions of load transistors are formed.

摘要翻译： 提供了一种制造半导体器件的方法，其实现了注入掩模的减少以及这种半导体器件。 通过使用抗蚀剂掩模和另一抗蚀剂掩模将硼注入NMOS区域作为注入掩模，形成用作存取晶体管和驱动晶体管的晕区的p型杂质区。 通过使用另一抗蚀剂掩模作为注入掩模将磷或砷进一步注入PMOS区，形成用作负载晶体管的晕区的n型杂质区。