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1.发明申请公开(公告)号：US20060047915A1
公开(公告)日：2006-03-02
申请号：US10933188
申请日：2004-09-01
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6024
摘要： A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
摘要翻译： 一种预取方案，用于检测何时加载错过较低级别的缓存，并触发下一级缓存。 因此，预取方案利用先前的信息将高速缓存未命中用于较低级别的高速缓存并且命中到下一个较高级别的高速缓冲存储器，这可能导致发起侧面预取负载，以将先前或下一个高速缓存行提取到下一级高速缓存 。 为了生成二进制预取的地址，在队列中保持高速缓存访问的历史。
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2.发明授权公开(公告)号：US07383418B2
公开(公告)日：2008-06-03
申请号：US10933188
申请日：2004-09-01
CPC分类号： G06F12/0897 , G06F12/0862 , G06F2212/6024
摘要： A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.
摘要翻译： 一种预取方案，用于检测何时加载错过较低级别的缓存，并触发下一级缓存。 因此，预取方案利用先前的信息将高速缓存未命中用于较低级别的高速缓存并且命中到下一个较高级别的高速缓冲存储器，这可能导致发起侧面预取负载，以将先前或下一个高速缓存行提取到下一级高速缓存 。 为了生成二进制预取的地址，在队列中保持高速缓存访问的历史。
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3.发明授权Processor and system using a mask register to track progress of gathering and prefetching elements from memory 有权处理器和系统使用掩码寄存器跟踪从内存中采集和预取元素的进度公开(公告)号：US08892848B2
公开(公告)日：2014-11-18
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译： 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。
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4.发明申请公开(公告)号：US20110099333A1
公开(公告)日：2011-04-28
申请号：US12908183
申请日：2010-10-20
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin
IPC分类号： G06F12/12
CPC分类号： G06F12/127 , G06F12/0862 , G06F12/124 , G06F2212/6028
摘要： A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.
摘要翻译： 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。
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5.发明授权Device, system, and method for improving processing efficiency by collectively applying operations 有权通过集体应用操作提高处理效率的装置，系统和方法公开(公告)号：US08681173B2
公开(公告)日：2014-03-25
申请号：US11967492
申请日：2007-12-31
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
IPC分类号： G09G5/00
CPC分类号： G06T1/20 , G06F9/3867
摘要： A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed.
摘要翻译： 一种用于生成包括两个或多个预定属性值的单个压缩向量的系统和方法。 对于诸如像素的多个数据点中的每一个，如果数据点的第一和第二属性值分别等于两个或更多个预定属性值的第一和第二属性值，则使用压缩向量 在数据点上操作。 描述和要求保护其他实施例。
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公开(公告)号：US08667250B2
公开(公告)日：2014-03-04
申请号：US11964631
申请日：2007-12-26
IPC分类号： G06F9/312
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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公开(公告)号：US20130232318A1
公开(公告)日：2013-09-05
申请号：US13844111
申请日：2013-03-15
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
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8.发明授权公开(公告)号：US08065488B2
公开(公告)日：2011-11-22
申请号：US12908183
申请日：2010-10-20
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin
IPC分类号： G06F12/12
CPC分类号： G06F12/127 , G06F12/0862 , G06F12/124 , G06F2212/6028
摘要： A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.
摘要翻译： 本文描述了用于有效地高速缓存流和非流数据的方法和装置。 诸如编译器的软件识别最后使用的流指令/操作，这些指令/操作是用于访问多个指令或一定时间量的最后指令/操作来访问流数据。 作为执行对最后使用指令/操作的高速缓存线的访问的结果，将高速缓存行更新为不再需要的流数据（SDN）状态。 当控制逻辑要确定要替换的高速缓存行时，修改的最近最少使用（LRU）算法被偏置以首先选择SDN状态行来替换不再需要的流数据。
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公开(公告)号：US20140019720A1
公开(公告)日：2014-01-16
申请号：US13762220
申请日：2013-02-07
IPC分类号： G06F9/30
CPC分类号： G06F9/30025 , G06F9/30036 , G06F9/30043
摘要： A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
摘要翻译： 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。
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10.发明申请DEVICE, SYSTEM, AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY 有权使用掩码寄存器跟踪记忆元素进度的设备，系统和方法公开(公告)号：US20110264863A1
公开(公告)日：2011-10-27
申请号：US13175953
申请日：2011-07-05
申请人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Tom Forsyth , Michael Abrash
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译： 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。
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