公开(公告)号：US06492669B2

公开(公告)日：2002-12-10

申请号：US09892567

申请日：2001-06-28

申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2980

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/7783

摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

摘要翻译： 在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。 在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。 载体供应层由AlGaN组成并具有拉伸应变。 肖特基层由InGaN组成并具有压应变。 在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

公开(公告)号：US06465814B2

公开(公告)日：2002-10-15

申请号：US09891419

申请日：2001-06-27

申请人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

发明人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

IPC分类号： H01L31072

CPC分类号： H01L29/7786 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

公开(公告)号：US06440822B1

公开(公告)日：2002-08-27

申请号：US09901424

申请日：2001-07-09

申请人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

发明人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

IPC分类号： H01L21301

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3677 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

摘要翻译： 在制造半导体器件的方法中，沟槽部分形成在衬底的相对表面部分之一的一侧上。 每个沟槽部分的一部分由形成在基板的一个表面部分上的电源金属层覆盖。 衬底被固定到支撑件，使得衬底的一个表面适合于支撑件。 使用沟槽部分将芯片与衬底分离。 在芯片的侧表面部分和芯片的另一个表面部分上形成导电膜。 然后，芯片与支架分离。

公开(公告)号：US06552373B2

公开(公告)日：2003-04-22

申请号：US09818587

申请日：2001-03-28

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

IPC分类号： H01L31072

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

摘要翻译： 异质结FET在电子供给层和n型盖层之间具有包括n型杂质掺杂层的中间层。 中间层通过离子化的正电荷抵消在电子供给层和n型覆盖层之间产生的极化的负电荷，从而减少对电子的阻挡和源极/漏极电阻。

公开(公告)号：US06441391B1

公开(公告)日：2002-08-27

申请号：US09940374

申请日：2001-08-29

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2906

CPC分类号： H01L29/812 ,  H01L29/045 ,  H01L29/2003

摘要： An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

摘要翻译： 本发明的目的是在III族氮化物半导体器件中提高元件高速运转中的生产率，散热特性和性能; 在其中A平面（（11-20）面）设置为基面的蓝宝石衬底上，形成III族氮化物半导体的外延生长层，并且在其上形成栅电极16，源电极 15和漏电极17; 这些电极被设置成使得它们被放置的方向相对于蓝宝石的C轴成20°以内的角度。

公开(公告)号：US06765241B2

公开(公告)日：2004-07-20

申请号：US10362883

申请日：2003-02-27

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L29812

CPC分类号： H01L29/8126 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003

摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.

摘要翻译： 具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。 该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。 在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。 所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

公开(公告)号：US06476431B1

公开(公告)日：2002-11-05

申请号：US09438840

申请日：1999-11-12

申请人： Yasuo Ohno ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi

发明人： Yasuo Ohno ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi

IPC分类号： H01L2980

CPC分类号： H01L29/812 ,  H01L29/1075

摘要： A p-type layer and an n-type layer which constitute a barrier layer are provided, and a leak of the holes at the time of the negative bias accompanying the p-type layer buffer required for the higher tolerance voltage is suppressed, and the discharge of the holes at the positive bias can be efficiently carried out. The tolerance voltage at the time of the OFF state is raised at the p-type layer buffer, and the tolerance voltage at the time of the ON state at the discharge of the holes is raised. Since no leak is generated from the p-type layer, the drain current is not lowered, and a higher output can be realized both in terms of the current and in terms of the voltage.

摘要翻译： 设置构成阻挡层的p型层和n型层，抑制伴随着较高公差电压所需的p型层缓冲器的负偏压时的空穴泄漏， 可以有效地进行正偏压下的孔的放电。 在p型层缓冲器处，断开状态时的公差电压升高，并且在孔的放电时的接通状态时的容许电压升高。 由于不会从p型层产生泄漏，所以漏极电流不降低，并且在电流和电压方面都可以实现更高的输出。

公开(公告)号：US06373082B1

公开(公告)日：2002-04-16

申请号：US09205707

申请日：1998-12-04

申请人： Yasuo Ohno ,  Yuji Takahashi ,  Kazuaki Kunihiro

发明人： Yasuo Ohno ,  Yuji Takahashi ,  Kazuaki Kunihiro

IPC分类号： H01L31119

CPC分类号： H01L23/4824 ,  H01L21/761 ,  H01L24/06 ,  H01L29/1029 ,  H01L29/42316 ,  H01L29/812 ,  H01L2224/48091 ,  H01L2924/12036 ,  H01L2924/1306 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/00014 ,  H01L2924/00

摘要： A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

摘要翻译： 一种化合物半导体场效应晶体管，其在栅电极和漏电极之间具有非栅极区，其为不被栅电极覆盖的沟道区，其中在非栅极区中形成多个隔离区 它们在沟道电流的方向上延伸并与栅电极接触的方式。 该化合物半导体场效应晶体管在漏极和栅极之间的击穿电压得到改善，并且保持了晶体管的高速可操作性。

公开(公告)号：US06278144B1

公开(公告)日：2001-08-21

申请号：US09248490

申请日：1999-02-10

申请人： Kazuaki Kunihiro ,  Yasuo Ohno ,  Yuji Takahashi

发明人： Kazuaki Kunihiro ,  Yasuo Ohno ,  Yuji Takahashi

IPC分类号： H01L2980

CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/8128

摘要： A high power FET has a first conductivity epitaxial layer overlying a semi-insulating substrate, a second conductivity epitaxial layer, a gate being in Schottky contact with the second conductivity layer, and source and drain regions being in ohmic contact with the second conductivity layer. Impurity concentration N2 and thickness D of the second conductivity layer are such that the following relationship holds: d > 2 ⁢ ϵ S ⁢ φ S eN 2 + 2 ⁢ ϵ S ⁢ V bi eN 2 ⁢ N 1 N 1 + N 2 wherein N1, is the impurity concentration of the first conductivity epitaxial layer, &phgr;s, &egr;s and Vbi, are surface potential, dielectric constant and a diffused potential, respectively, of the second conductivity epitaxial layer, and e is an elementary charge of electron. An electrically neutral region is formed in the second conductivity epitaxial layer when no voltage is applied between the gate and the source region, whereby the electrically neutral region functions similarly to the gate of a cascode-connected MOSFET, which improves the breakdown voltage of the FET.

摘要翻译： 高功率FET具有覆盖半绝缘衬底的第一导电外延层，第二导电外延层，与第二导电层肖特基接触的栅极，以及与第二导电层欧姆接触的源极和漏极区。 第二导电层的杂质浓度N2和厚度D使得以下关系成立：其中N1是第一导电外延层的杂质浓度，phis，εis和Vbi，是表面电位，介电常数和扩散电位， 分别是第二导电外延层，e是电子的基本电荷。 当在栅极和源极区之间没有施加电压时，在第二导电外延层中形成电中性区域，由此电中性区域类似于共源共栅MOSFET的栅极起作用，这改善了FET的击穿电压 。

公开(公告)号：US06180968B2

公开(公告)日：2001-01-30

申请号：US08866268

申请日：1997-05-30

申请人： Kensuke Kasahara ,  Yasuo Ohno ,  Satoru Ohkubo

发明人： Kensuke Kasahara ,  Yasuo Ohno ,  Satoru Ohkubo

IPC分类号： H01L31072

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/7783

摘要： There are provided a compound semiconductor device having a semiconductor multilayered structure, and a method of manufacturing the same. The semiconductor multilayered structure consists of a first recess etching stopper formed on a conductive layer of a compound semiconductor, a first semiconductor layer formed on the first recess etching stopper layer, a second recess etching stopper layer formed on the first semiconductor layer, and a second semiconductor layer formed on the second recess etching stopper layer.

摘要翻译： 提供了具有半导体多层结构的化合物半导体器件及其制造方法。 半导体多层结构由形成在化合物半导体的导电层上的第一凹部蚀刻止动件，形成在第一凹部蚀刻停止层上的第一半导体层，形成在第一半导体层上的第二凹部蚀刻停止层，以及第二凹部蚀刻阻挡层 半导体层形成在第二凹槽蚀刻阻挡层上。