公开(公告)号：US06441391B1

公开(公告)日：2002-08-27

申请号：US09940374

申请日：2001-08-29

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2906

CPC分类号： H01L29/812 ,  H01L29/045 ,  H01L29/2003

摘要： An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.

摘要翻译： 本发明的目的是在III族氮化物半导体器件中提高元件高速运转中的生产率，散热特性和性能; 在其中A平面（（11-20）面）设置为基面的蓝宝石衬底上，形成III族氮化物半导体的外延生长层，并且在其上形成栅电极16，源电极 15和漏电极17; 这些电极被设置成使得它们被放置的方向相对于蓝宝石的C轴成20°以内的角度。

公开(公告)号：US06765241B2

公开(公告)日：2004-07-20

申请号：US10362883

申请日：2003-02-27

申请人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

发明人： Yasuo Ohno ,  Nobuyuki Hayama ,  Kensuke Kasahara ,  Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yuji Takahashi ,  Yuji Ando ,  Kohji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L29812

CPC分类号： H01L29/8126 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/2003

摘要： A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1). t sub ≦ 10 ⁢ ϵ sub ⁢ S pad ϵ epi ⁢ S gate ⁢ t act where Spad is an area of the pad electrode; Sgate is an area of the gate electrode; &egr;sub is a relative permittivity of the sapphire substrate in the direction of the thickness; &egr;epi is a relative permittivity of the group III nitride semiconductor layer in the direction of the thickness; tsub is a thickness of the sapphire substrate; and tact is an effective thickness of the group III nitride semiconductor layer.

摘要翻译： 具有提高生产率的场效应晶体管类型的III族氮化物半导体器件，适于在高速操作中优异的器件性能以及良好的热扩散特性的减小的寄生电容。 该器件包括形成在蓝宝石的A平面（（11-20）面）上的具有缓冲层的III族氮化物半导体的外延生长层。 在其上形成栅电极，源电极，漏电极和焊盘电极，并且在蓝宝石衬底的背面上形成接地导体层。 所述蓝宝石衬底tsub的厚度满足以下等式（1）。其中，Spad是焊盘电极的面积; Sgate是栅电极的面积; epsilonsub是蓝宝石衬底在厚度方向上的相对介电常数;εilon 是III族氮化物半导体层在厚度方向上的相对介电常数; tsub是蓝宝石衬底的厚度; andtact是III族氮化物半导体层的有效厚度。

公开(公告)号：US06465814B2

公开(公告)日：2002-10-15

申请号：US09891419

申请日：2001-06-27

申请人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

发明人： Kensuke Kasahara ,  Yasuo Ohno ,  Masaaki Kuzuhara ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuaki Kunihiro ,  Nobuyuki Hayama ,  Yuji Takahashi ,  Kouji Matsunaga

IPC分类号： H01L31072

CPC分类号： H01L29/7786 ,  H01L21/28575 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device of the present invention comprises Al0.3Ga0.7N layer 4 and Al0.1Ga0.9N layer 5 having different Al contents as an electron supply layer on GaN layer 6 serving as an active layer. An area where Al0.3Ga0.7N layer 4 is formed is used as a low resistance area, while an area where Al0.1Ga0.9N layer 5 is formed is used as a high resistance area. As a result, a distribution of two-dimensional electrons serving as carriers is produced within a horizontal plane perpendicular to the thickness direction of the layers to form a desired device configuration. For example, when the configuration is applied to a transistor configuration, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, and at the same time, a channel concentration in source and drain areas is increased to realize low contact resistance.

公开(公告)号：US06440822B1

公开(公告)日：2002-08-27

申请号：US09901424

申请日：2001-07-09

申请人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

发明人： Nobuyuki Hayama ,  Masaaki Kuzuhara ,  Kouji Matsunaga ,  Tatsuo Nakayama ,  Yuji Takahashi ,  Yasuo Ohno ,  Kazuaki Kunihiro ,  Kensuke Kasahara ,  Hironobu Miyamoto ,  Yuji Ando

IPC分类号： H01L21301

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3677 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, trench sections are formed on a side of one of opposing surface portions of a substrate. At lest a part of each of the trench sections is covered by a power supply metal layer which is formed on the one surface portion of the substrate. The substrate is fixed to a support such that the one surface of the substrate fits to the support. A chip is separated from the substrate using the trench sections. A conductive film is formed on side surface portions of the chip and the other surface portion of the chip. Then, the chip is separated from the support.

摘要翻译： 在制造半导体器件的方法中，沟槽部分形成在衬底的相对表面部分之一的一侧上。 每个沟槽部分的一部分由形成在基板的一个表面部分上的电源金属层覆盖。 衬底被固定到支撑件，使得衬底的一个表面适合于支撑件。 使用沟槽部分将芯片与衬底分离。 在芯片的侧表面部分和芯片的另一个表面部分上形成导电膜。 然后，芯片与支架分离。

公开(公告)号：US06492669B2

公开(公告)日：2002-12-10

申请号：US09892567

申请日：2001-06-28

申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Kensuke Kasahara ,  Nobuyuki Hayama ,  Yasuo Ohno ,  Kouji Matsunaga ,  Masaaki Kuzuhara

IPC分类号： H01L2980

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/475 ,  H01L29/7783

摘要： A carrier travel layer is formed on the substrate of a semiconductor device with a buffer layer interposed, and a spacer layer and carrier supply layer are then formed on this carrier travel layer. On the carrier supply layer are provided a source electrode and a drain electrode, and a gate electrode is provided on an interposed Schottky layer. The carrier supply layer is composed of AlGaN and has tensile strain. The Schottky layer is composed of InGaN and has compressive strain. A negative piezoelectric charge is induced on the carrier supply layer side of the Schottky layer, and a positive piezoelectric charge is induced on the opposite side of the Schottky layer, whereby a sufficient Schottky barrier height is obtained and leakage current is suppressed.

摘要翻译： 在具有缓冲层的半导体器件的基板上形成载流子行进层，然后在该载体行进层上形成间隔层和载体供给层。 在载体供给层上设置有源电极和漏电极，在插入的肖特基层上设置有栅电极。 载体供应层由AlGaN组成并具有拉伸应变。 肖特基层由InGaN组成并具有压应变。 在肖特基层的载流子供给层侧感应出负的压电电荷，在肖特基层的相反侧产生正的压电电荷，由此获得足够的肖特基势垒高度，并且抑制泄漏电流。

公开(公告)号：US06552373B2

公开(公告)日：2003-04-22

申请号：US09818587

申请日：2001-03-28

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Naotaka Iwata ,  Koji Matsunaga ,  Masaaki Kuzuhara ,  Kensuke Kasahara ,  Kazuaki Kunihiro ,  Yuji Takahashi ,  Tatsuo Nakayama ,  Nobuyuki Hayama ,  Yasuo Ohno

IPC分类号： H01L31072

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： A hetero-junction FET has an intermediate layer including n-type-impurity doped layer between an electron supply layer and an n-type cap layer. The intermediate layer cancels the polarized negative charge generated between the electron supply layer and the n-type cap layer by ionized positive charge, thereby reducing the barrier against the electrons and source/drain resistance.

摘要翻译： 异质结FET在电子供给层和n型盖层之间具有包括n型杂质掺杂层的中间层。 中间层通过离子化的正电荷抵消在电子供给层和n型覆盖层之间产生的极化的负电荷，从而减少对电子的阻挡和源极/漏极电阻。

公开(公告)号：US20110291158A1

公开(公告)日：2011-12-01

申请号：US13138410

申请日：2010-02-12

申请人： Mutsuo Ogura ,  SungWoo Choi ,  Nobuyuki Hayama ,  Katsuhiko Nishida

发明人： Mutsuo Ogura ,  SungWoo Choi ,  Nobuyuki Hayama ,  Katsuhiko Nishida

IPC分类号： H01L31/0352

CPC分类号： H01L31/03046 ,  H01L31/1105 ,  Y02E10/544

摘要： The present invention provides a HPT having high sensitivity and extensive wavelength band characteristics. The collector and barrier layer (5) is formed on the photo-absorption layer (6), wherein the energy level in the conduction band is higher than that of the photo-absorption layer (6), the energy level in the valence band is almost equal to or higher than that of the photo-absorption layer (6) and is a relatively wider gap semiconductor than the photo-absorption layer. The base layer (4) formed on the collector and barrier layer (5), is a relatively narrow gap as compared with the collector and barrier layer (5), wherein the energy level in the conduction band is equal to or higher than that of the collector and barrier layer (5) in the boundary of the collector and barrier layer (5). The emitter layer (3) formed on a base layer (4) is a relatively wide gap as compared with the base layer (4), and the energy level in the valence band is the first conductivity type semiconductor layer lower than that of the base layer (4).

摘要翻译： 本发明提供具有高灵敏度和广泛波长带特性的HPT。 在光吸收层（6）上形成集电极和阻挡层（5），其中导带中的能级高于光吸收层（6）的能级，价带中的能级为 几乎等于或高于光吸收层（6），并且是比光吸收层更宽的间隙半导体。 形成在集电极和阻挡层（5）上的基底层（4）与集电极和阻挡层（5）相比是相对窄的间隙，其中导带中的能级等于或高于 在集电体和阻挡层（5）的边界中的集电极和阻挡层（5）。 形成在基底层（4）上的发射极层（3）与基底层（4）相比是相对较宽的间隙，并且价带中的能级是第一导电类型半导体层低于基底层 层（4）。

公开(公告)号：US06507089B1

公开(公告)日：2003-01-14

申请号：US09589681

申请日：2000-06-07

申请人： Kouji Azuma ,  Nobuyuki Hayama ,  Norio Goto

发明人： Kouji Azuma ,  Nobuyuki Hayama ,  Norio Goto

IPC分类号： H01L27082

CPC分类号： H01L27/082 ,  H03K17/08146

摘要： A semiconductor device is provided with a plurality of hetero junction bipolar transistors arranged in a specified direction. Also, the semiconductor device comprises emitter wiring connected to each emitter of the plural hetero junction bipolar transistors, collector wiring connected to each collector of said plural hetero junction bipolar transistors, and base wiring connected to at least one base of said plural hetero junction bipolar transistors. Bases that are not connected to the base wiring among the bases of the plural hetero junction bipolar transistors are connected to the emitter wiring.

摘要翻译： 半导体器件设置有沿指定方向布置的多个异质结双极晶体管。 此外，半导体器件包括连接到多个异质结双极晶体管的每个发射极的发射极布线，连接到所述多个异质结双极晶体管的每个集电极的集电极布线，以及连接到所述多个异质结双极晶体管的至少一个基极的基极布线 。 在多个异质结双极晶体管的基极之间未连接到基极布线的基极连接到发射极布线。

公开(公告)号：US09076906B2

公开(公告)日：2015-07-07

申请号：US13138410

申请日：2010-02-12

申请人： Mutsuo Ogura ,  SungWoo Choi ,  Nobuyuki Hayama ,  Katsuhiko Nishida

发明人： Mutsuo Ogura ,  SungWoo Choi ,  Nobuyuki Hayama ,  Katsuhiko Nishida

IPC分类号： H01L31/102 ,  H01L31/0304 ,  H01L31/11

CPC分类号： H01L31/03046 ,  H01L31/1105 ,  Y02E10/544

摘要： A hetero-junction bipolar phototransistor includes a photo-absorption layer formed of a first conductivity type semiconductor layer, and a collector operating as a barrier layer, a base layer, and an emitter layer, which are stacked in sequence on the photo-absorption layer. The photo-absorption layer, collector, base layer and emitter layer forms a first mesa structure, and an emitter contact layer forms a second mesa structure. The photo-absorption layer includes a semiconductor layer with a narrow gap corresponding to a light-sensing wavelength of the phototransistor. The collector includes a semiconductor layer with a wider gap than a gap of the photo-absorption layer. The base layer has an energy level equal to or higher than the energy level of the collector. The emitter layer has a wide gap as compared to the base layer, and an energy level in a valence band is lower than an energy level of the base layer.

摘要翻译： 异质结双极性光电晶体管包括由第一导电型半导体层形成的光吸收层和作为阻挡层，基极层和发射极层的集电体，其顺序层叠在光吸收层上 。 光吸收层，集电体，基极层和发射极层形成第一台面结构，并且发射极接触层形成第二台面结构。 光吸收层包括具有对应于光电晶体管的感光波长的窄间隙的半导体层。 集电体包括具有比光吸收层的间隙更宽的间隙的半导体层。 基层具有等于或高于集电极能级的能级。 发射极层与基底层相比具有宽的间隙，并且价带中的能级低于基底层的能级。

公开(公告)号：US4217783A

公开(公告)日：1980-08-19

申请号：US12376

申请日：1979-02-15

申请人： Susumu Ito ,  Morimasa Nagao ,  Toshio Yamagata ,  Nobuyuki Hayama

发明人： Susumu Ito ,  Morimasa Nagao ,  Toshio Yamagata ,  Nobuyuki Hayama

IPC分类号： G01L9/00 ,  G01L9/16 ,  G01L9/04

CPC分类号： G01L9/16 ,  G01L9/0051

摘要： A pressure sensor comprises essentially magnetoresistive elements formed on a diaphragm serving as a stress magnifier. The diaphragm may be made, for example, of glass in a thickness of 0.5 millimeter, and the magnetoresistive elements can be formed thereon in any desired pattern of thin stripes by ordinary thin-film techniques. Such sensor elements can be mass produced, e.g., by vapor deposition and etching on a large sheet of diaphragm material and cutting into chips of desired shape and size.

摘要翻译： 压力传感器包括基本上形成在用作应力放大器的隔膜上的磁阻元件。 隔膜可以由例如0.5mm厚的玻璃制成，并且可以通过普通薄膜技术以任何所需的薄条纹图案在其上形成磁阻元件。 这样的传感器元件可以例如通过在大片隔膜材料上的气相沉积和蚀刻而大量生产并切割成所需形状和尺寸的芯片。