公开(公告)号：US08436687B2

公开(公告)日：2013-05-07

申请号：US12974996

申请日：2010-12-21

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H03K3/03

CPC分类号： H03K3/354

摘要： An oscillating apparatus includes: a transfer gate including a P-channel transistor and a N-channel transistor; a first inverter for inverting an output signal of the transfer gate and outputting the inverted output signal of the transfer gate; a second inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a third inverter for inverting the output signal of the first inverter and outputting the inverted output signal of the first inverter; a fourth inverter for inverting the output signal of the third inverter and outputting the inverted output signal of the third inverter to an input-terminal of the transfer gate; a first capacitor connected between an output-terminal of the transfer gate and an output-terminal of the second inverter; and a second capacitor connected between the output-terminal of the transfer gate and a reference potential node.

摘要翻译： 振荡装置包括：传输门，包括P沟道晶体管和N沟道晶体管; 第一反相器，用于反转传输门的输出信号并输出​​转移门的反相输出信号; 第二逆变器，用于反相第一反相器的输出信号，并输出第一反相器的反相输出信号; 第三反相器，用于反相第一反相器的输出信号并输出​​第一反相器的反相输出信号; 第四反相器，用于反相第三反相器的输出信号，并将第三反相器的反相输出信号输出到传输门的输入端; 连接在所述传输门的输出端和所述第二反相器的输出端之间的第一电容器; 以及连接在传输门的输出端和参考电位节点之间的第二电容器。

公开(公告)号：US20120075128A1

公开(公告)日：2012-03-29

申请号：US13186059

申请日：2011-07-19

申请人： Kenta ARUGA ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

发明人： Kenta ARUGA ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

IPC分类号： H03M1/12

CPC分类号： H03M1/1038 ,  H03M1/1019 ,  H03M1/144 ,  H03M1/468 ,  H03M1/765 ,  H03M1/804

摘要： A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

摘要翻译： 逐次逼近A / D转换器，具有耦合到顶部节点和开关组的电容元件组的主DAC; 比较上位节点电压和比较参考电压的比较器; 校正DAC根据要在主DAC中平衡的电容元件对的电容误差产生校正电压，并向顶部节点提供校正电压; 以及控制电路，产生用于控制开关组的内部数字输入和用于控制校正电压的校正码，并且当执行A / D转换时，通过比较器输出逐次逼近结果。 控制电路测量要平衡的电容元件对的电容误差，并确定偏移消除的电容误差，其中在测量中产生的偏移从电容误差中消除。

公开(公告)号：US07948304B2

公开(公告)日：2011-05-24

申请号：US12619496

申请日：2009-11-16

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A constant-voltage generating circuit includes: a reference potential generating unit; first and second amplifier units whose outputs are respectively connected to the output line; and a low-pass filter, and wherein first and second operation periods are repeated, one alternating with the other, the first amplifier unit stores offset voltage of the first amplifier unit during the second operation period, and produces an output, during the first operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage, and the second amplifier unit stores offset voltage of the second amplifier unit during the first operation period, and produces an output, during the second operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage.

摘要翻译： 恒压发生电路包括：基准电位发生单元; 第一和第二放大器单元，其输出分别连接到输出线; 和低通滤波器，并且其中重复第一和第二操作周期，一个与另一个交替，第一放大器单元在第二操作周期期间存储第一放大器单元的偏移电压，并且在第一操作期间产生输出 周期，其通过使用所存储的偏移电压消除偏移电压使第一电位和第二电位彼此相等，并且第二放大器单元在第一操作周期期间存储第二放大器单元的偏移电压，并且产生输出 在第二操作期间，通过使用存储的偏移电压消除偏移电压，使第一电位和第二电位彼此相等。

公开(公告)号：US08786358B2

公开(公告)日：2014-07-22

申请号：US13036956

申请日：2011-02-28

申请人： Yoshiyuki Endo ,  Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Yoshiyuki Endo ,  Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： G05F1/10 ,  G05F3/24

CPC分类号： G05F3/245 ,  G05F3/30

摘要： A reference voltage circuit includes a first amplifier configured to output a reference voltage, a second amplifier coupled to the first amplifier, an offset adjustment voltage generation circuit, a first load device and a first pn junction device, and second and third load devices and a second pn junction device. The offset adjustment voltage generation circuit is configured to generate a voltage which is input to the third and fourth input terminals of the second amplifier, and reduce an offset voltage between the first and second input terminals of the first amplifier through the second amplifier. The first input terminal is coupled to a coupling node of the first load device and the first pn junction device, and the second input terminal is coupled to a coupling node of the second load device and the third load device.

摘要翻译： 参考电压电路包括被配置为输出参考电压的第一放大器，耦合到第一放大器的第二放大器，偏移调整电压产生电路，第一负载装置和第一pn结装置，以及第二和第三负载装置和 第二个pn连接装置。 偏移调整电压产生电路被配置为产生输入到第二放大器的第三和第四输入端的电压，并且通过第二放大器减小第一放大器的第一和第二输入端之间的偏移电压。 第一输入端耦合到第一负载装置和第一pn结装置的耦合节点，并且第二输入端耦合到第二负载装置和第三负载装置的耦合节点。

公开(公告)号：US08519874B2

公开(公告)日：2013-08-27

申请号：US13186059

申请日：2011-07-19

申请人： Kenta Aruga ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Sanroku Tsukamoto ,  Koji Okada

IPC分类号： H03M1/10 ,  H03M1/14

CPC分类号： H03M1/1038 ,  H03M1/1019 ,  H03M1/144 ,  H03M1/468 ,  H03M1/765 ,  H03M1/804

摘要： A successive approximation A/D converter, has a main DAC having a capacitive element group coupled to a top node and a switch group; a comparator comparing voltage of the top node with comparison reference voltage; a correction DAC generating correction voltage in accordance with a capacitance error of a capacitive element pair to be balanced in the main DAC, and supplying the correction voltage to the top node; and a control circuit generating internal digital input for controlling the switch group and a correction code for controlling the correction voltage, and outputting a successive approximation result by the comparator when the A/D conversion is performed. The control circuit measures a capacitance error of the capacitive element pair to be balanced, and determines an offset-removed capacitance error where an offset generated in the measurement is removed from the capacitance error.

摘要翻译： 逐次逼近A / D转换器，具有耦合到顶部节点和开关组的电容元件组的主DAC; 比较上位节点电压和比较参考电压的比较器; 校正DAC根据要在主DAC中平衡的电容元件对的电容误差产生校正电压，并向顶部节点提供校正电压; 以及控制电路，产生用于控制开关组的内部数字输入和用于控制校正电压的校正码，并且当执行A / D转换时，通过比较器输出逐次逼近结果。 控制电路测量要平衡的电容元件对的电容误差，并确定偏移消除的电容误差，其中在测量中产生的偏移从电容误差中消除。

公开(公告)号：US20100133589A1

公开(公告)日：2010-06-03

申请号：US12617608

申请日：2009-11-12

申请人： Kenta ARUGA ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta ARUGA ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H01L25/03

CPC分类号： H01L27/092 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/085 ,  H01L27/105 ,  H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

摘要： An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

摘要翻译： 模拟电路单元阵列包括排列成阵列的多个晶体管单元。 每个晶体管单元包括第一源极区域，第一沟道区域，公共漏极区域，第二沟道区域和与另一个相邻布置的第二源极区域; 以及分别形成在所述第一沟道区域和所述第二沟道区域上的第一栅极电极和第二栅极电极，并且其中所述第一栅极电极和所述第二栅极电极连接在一起使用，并且所述第一源极区域和所述第二源极 区域连接在一起使用。

公开(公告)号：US20100001892A1

公开(公告)日：2010-01-07

申请号：US12409462

申请日：2009-03-23

申请人： Kenta ARUGA ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta ARUGA ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H03M1/12

CPC分类号： H03M1/1047 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/687 ,  H03M1/765 ,  H03M1/804

摘要： A successive approximation A/D converter includes a capacitive D/A converter including capacitors, and generates a voltage based on the input voltage and a first digital signal including J bits; a resistive D/A converter that generates a voltage based on a second digital signal; a capacitor that capacity-couples the voltage to an output node; a comparator that generates a result based on the voltage; a control circuit that supplies the first digital signal to the capacitive D/A converter according to the result and outputs a third digital signal indicating a correction and a fourth digital signal including K bits; and a digital calculating circuit that generates the second digital signal including K bits based on the third digital signal and the fourth digital signal, and supplies the second digital signal to the resistive D/A converter, a (J+K) bit digital data is generated based on the input signal.

摘要翻译： 逐次逼近A / D转换器包括具有电容器的电容式D / A转换器，并且基于输入电压产生电压和包括J位的第一数字信号; 电阻式D / A转换器，其基于第二数字信号产生电压; 将电压耦合到输出节点的电容器; 基于电压产生结果的比较器; 控制电路，根据结果将第一数字信号提供给电容性D / A转换器，并输出指示校正的第三数字信号和包括K位的第四数字信号; 以及数字计算电路，其基于第三数字信号和第四数字信号生成包括K位的第二数字信号，并将第二数字信号提供给电阻性D / A转换器，（J + K）位数字数据 基于输入信号生成。

公开(公告)号：US07928871B2

公开(公告)日：2011-04-19

申请号：US12409462

申请日：2009-03-23

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H03M1/06

CPC分类号： H03M1/1047 ,  H03M1/0682 ,  H03M1/468 ,  H03M1/687 ,  H03M1/765 ,  H03M1/804

摘要： A successive approximation A/D converter includes a capacitive D/A converter including capacitors, and generates a voltage based on the input voltage and a first digital signal including J bits; a resistive D/A converter that generates a voltage based on a second digital signal; a capacitor that capacity-couples the voltage to an output node; a comparator that generates a result based on the voltage; a control circuit that supplies the first digital signal to the capacitive D/A converter according to the result and outputs a third digital signal indicating a correction and a fourth digital signal including K bits; and a digital calculating circuit that generates the second digital signal including K bits based on the third digital signal and the fourth digital signal, and supplies the second digital signal to the resistive D/A converter, a (J+K) bit digital data is generated based on the input signal.

摘要翻译： 逐次逼近A / D转换器包括具有电容器的电容式D / A转换器，并且基于输入电压产生电压和包括J位的第一数字信号; 电阻式D / A转换器，其基于第二数字信号产生电压; 将电压耦合到输出节点的电容器; 基于电压产生结果的比较器; 控制电路，根据结果将第一数字信号提供给电容性D / A转换器，并输出指示校正的第三数字信号和包括K位的第四数字信号; 以及数字计算电路，其基于第三数字信号和第四数字信号生成包括K位的第二数字信号，并将第二数字信号提供给电阻性D / A转换器，（J + K）位数字数据 基于输入信号生成。

公开(公告)号：US20100188141A1

公开(公告)日：2010-07-29

申请号：US12619496

申请日：2009-11-16

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： A constant-voltage generating circuit includes: a reference potential generating unit; first and second amplifier units whose outputs are respectively connected to the output line; and a low-pass filter, and wherein first and second operation periods are repeated, one alternating with the other, the first amplifier unit stores offset voltage of the first amplifier unit during the second operation period, and produces an output, during the first operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage, and the second amplifier unit stores offset voltage of the second amplifier unit during the first operation period, and produces an output, during the second operation period, that brings the first potential and the second potential equal to each other by canceling out the offset voltage using the stored offset voltage.

摘要翻译： 恒压发生电路包括：基准电位发生单元; 第一和第二放大器单元，其输出分别连接到输出线; 和低通滤波器，并且其中重复第一和第二操作周期，一个与另一个交替，第一放大器单元在第二操作周期期间存储第一放大器单元的偏移电压，并且在第一操作期间产生输出 周期，其通过使用所存储的偏移电压消除偏移电压使第一电位和第二电位彼此相等，并且第二放大器单元在第一操作周期期间存储第二放大器单元的偏移电压，并且产生输出 在第二操作期间，通过使用存储的偏移电压消除偏移电压，使第一电位和第二电位彼此相等。

公开(公告)号：US08368577B2

公开(公告)日：2013-02-05

申请号：US13036429

申请日：2011-02-28

申请人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

发明人： Kenta Aruga ,  Suguru Tachibana ,  Koji Okada

IPC分类号： H03M1/10

CPC分类号： H03M1/06 ,  H01L23/5223 ,  H01L23/5225 ,  H01L28/86 ,  H01L29/94 ,  H01L2924/0002 ,  H03M1/1047 ,  H03M1/468 ,  H03M1/687 ,  H03M1/765 ,  H03M1/804 ,  H01L2924/00

摘要： An A/D converter includes a capacitive DAC configured to perform conversion of high-order bits by receiving a differential signal, a resistive DAC configured to perform conversion of low-order bits, a resistive correction DAC configured to operate to correct the capacitive DAC, and a comparator. The capacitive DAC includes a positive-side capacitive DAC and a negative-side capacitive DAC operating in a complementary fashion, and the comparator, which includes a plurality of differential circuits, is configured to compare output potentials of the positive-side capacitive DAC and the negative-side capacitive DAC. The positive-side capacitive DAC and the negative-side capacitive DAC include first capacitive elements each formed from interconnect layers excluding an uppermost interconnect layer, and the comparator includes second capacitive elements each provided between adjacent ones of the differential circuits and formed from interconnect layers including the uppermost interconnect layer.

摘要翻译： A / D转换器包括配置为通过接收差分信号来执行高阶位的转换的电容性DAC，被配置为执行低位的转换的电阻式DAC，被配置为操作以校正电容性DAC的电阻校正DAC， 和比较器。 电容DAC包括以互补方式工作的正侧电容DAC和负侧电容DAC，并且包括多个差分电路的比较器被配置为将正侧电容DAC的输出电位和 负侧电容式DAC。 正侧电容式DAC和负侧电容式DAC包括由不包括最上层互连层的互连层形成的第一电容性元件，并且比较器包括第二电容性元件，每个电容元件设置在相邻的差分电路之间， 最上层的互连层。