公开(公告)号：US20110231593A1

公开(公告)日：2011-09-22

申请号：US12958298

申请日：2010-12-01

申请人： Kenta YASUFUKU ,  Shigeaki IWASA ,  Yasuhiko KUROSAWA ,  Hiroo HAYASHI ,  Seiji MAEDA ,  Mitsuo SAITO

发明人： Kenta YASUFUKU ,  Shigeaki IWASA ,  Yasuhiko KUROSAWA ,  Hiroo HAYASHI ,  Seiji MAEDA ,  Mitsuo SAITO

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F13/28

CPC分类号： G06F12/1063 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/1054 ,  G06F12/1081 ,  G06F12/12 ,  Y02D10/13

摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。

公开(公告)号：US20090019225A1

公开(公告)日：2009-01-15

申请号：US12038467

申请日：2008-02-27

申请人： Seiji MAEDA

发明人： Seiji MAEDA

IPC分类号： G06F12/00

CPC分类号： G06F8/4442 ,  G06F12/0875 ,  G06F12/0895

摘要： With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instruction having a possibility of using mutually the same cache line in a cache memory when mutually different cache lines in a main memory are accessed, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated.

摘要翻译： 关于包含在内部表示程序中的存储器访问指令，信息处理装置生成与根据所述内部表示程序执行的判断处理的结果相对应地执行的加载高速缓存指令，高速缓存命中判定指令和高速缓存未命中指令 缓存命中判断指令。 在内部表示程序包含多个存储器访问指令的情况下，该存储器访问指令具有在主存储器中相互不同的高速缓存行被访问时在高速缓冲存储器中使用相互相同的高速缓存行的可能性，所述信息处理设备生成组合指令 根据高速缓存命中判断指令执行的判断处理的判定结果应该合并为一个判断结果。 信息处理装置输出包含已经生成的这些指令的输出程序。

公开(公告)号：US20090143641A1

公开(公告)日：2009-06-04

申请号：US12023782

申请日：2008-01-31

申请人： Seiji MAEDA ,  Akihito KANO

发明人： Seiji MAEDA ,  Akihito KANO

IPC分类号： A61B1/018

CPC分类号： A61B1/122 ,  A61B1/00135 ,  A61B1/313 ,  A61B18/1492

摘要： A harvesting device for an endoscope includes a harvesting member inserted through an outer tube member, including a harvesting portion arranged at the distal end portion of the outer tube member and to perform a harvesting, and configured to move so that the harvesting member moves and positions the harvesting portion at a harvesting position and a standby position, a wipe member inserted through the outer tube member, including a wipe portion arranged at the distal end portion of the outer tube member, and configured to move so that the wipe member moves the wipe portion to wipe a distal end portion of the endoscope, and a conversion mechanism to convert the movement of the harvesting member into that of the wipe member to interlock the wiping of the wipe portion with the positioning of the harvesting portion.

摘要翻译： 用于内窥镜的收获装置包括：插入穿过外管构件的收获构件，包括设置在外管构件的远端部分处的收获部分并执行收获，并且构造成移动，使得收获构件移动并且位置 在采收位置和备用位置处的收获部分，穿过外管构件插入的擦拭构件，包括布置在外管构件的远端部分处的擦拭部分，并且构造成移动，使得擦拭构件移动擦拭物 用于擦拭内窥镜的远端部分的部分，以及转换机构，用于将收获部件的运动转换成擦拭部件的运动，以使得擦拭部分的擦拭与捕获部分的定位互锁。

公开(公告)号：US20080301415A1

公开(公告)日：2008-12-04

申请号：US12047835

申请日：2008-03-13

申请人： Seiji MAEDA ,  Hidenori Matsuzaki ,  Yusuke Shirota ,  Kazuya Kitsunai

发明人： Seiji MAEDA ,  Hidenori Matsuzaki ,  Yusuke Shirota ,  Kazuya Kitsunai

IPC分类号： G06F9/30

CPC分类号： G06F9/455 ,  G06F9/45504

摘要： An information processing system includes a first processor that accesses a first memory, a second processor that accesses a second memory, and a data transfer unit for executing data transfer between the first memory and the second memory. The first processor executes functions of translating an instruction out of instructions included in the program except a memory access instruction into an instruction for the second processor and translating the memory access instruction into an instruction sequence containing a call instruction of the program to transfer the access data on the first memory to the second memory via a data transfer unit.

摘要翻译： 信息处理系统包括访问第一存储器的第一处理器，访问第二存储器的第二处理器，以及用于在第一存储器和第二存储器之间执行数据传送的数据传送单元。 第一处理器执行将除了存储器访问指令之外的包括在程序中的指令的指令转换成用于第二处理器的指令的功能，并将存储器访问指令转换为包含程序的调用指令以传送访问数据的指令序列 通过数据传送单元将第一存储器存储到第二存储器。

公开(公告)号：US20120131909A1

公开(公告)日：2012-05-31

申请号：US13305285

申请日：2011-11-28

申请人： Seiji MAEDA

发明人： Seiji MAEDA

IPC分类号： F01N11/00 ,  G01N27/407

CPC分类号： G01N27/4065 ,  F02D41/1454 ,  F02D41/1495 ,  G01N27/4175

摘要： A control apparatus (100) for a gas sensor (10) which includes a cell (2) composed of a solid electrolyte body and a pair of electrodes provided thereon. The control apparatus includes voltage application means (70) for applying a single pulse voltage to the cell over a constant energization time T; first-output-value obtaining means 70 for obtaining a first output value Vri1 from the cell when a first time t1 shorter than the constant energization time has elapsed; second-output-value obtaining means (70) for obtaining a second output value Vri2 from the cell when a second time t2 shorter than the constant energization time but longer than the first time has elapsed; and deterioration-degree detection means 70 for detecting the degree of deterioration of the cell on the basis of a difference ΔVri between the second output value and the first output value.

摘要翻译： 一种用于气体传感器（10）的控制装置（100），其包括由固体电解质体和设置在其上的一对电极组成的电池（2）。 控制装置包括用于在恒定的通电时间T下向单元施加单脉冲电压的电压施加装置（70） 第一输出值获取装置70，用于当经过比恒定通电时间短的第一时间t1时，从单元获得第一输出值Vri1; 第二输出值获取装置，用于当第二时间t2短于恒定通电时间但长于第一时间时，从单元获得第二输出值Vri2; 以及劣化度检测装置70，用于基于第二输出值和第一输出值之间的差Dgr; Vri检测单元的劣化程度。

公开(公告)号：US20110174615A1

公开(公告)日：2011-07-21

申请号：US13009261

申请日：2011-01-19

申请人： Seiji MAEDA

发明人： Seiji MAEDA

IPC分类号： G01N27/30

CPC分类号： F02D41/14 ,  G01N27/4175

摘要： A deterioration signal generation device for an oxygen sensor having a power supply different than a power supply connected to an external device, including a connection unit for electrically connecting the ground lines of the respective power supplies; a first acquisition unit for electrically connecting to a first output line at a reference potential side and to a second output line at a sensor potential side of the oxygen sensor, to obtain first and second potentials, respectively; an operation unit that calculates a first differential value between the first and second potentials; a processing unit that performs an operation on the first differential value; a second acquisition unit that acquires a third potential of a first input line at a reference potential side of the external device; and an output unit that generates the deterioration signal by superposing the second differential value on the third potential.

摘要翻译： 一种用于氧传感器的劣化信号产生装置，其具有不同于连接到外部装置的电源的电源，包括用于电连接各个电源的接地线的连接单元; 第一获取单元，用于电连接到氧传感器的传感器电位侧的参考电位侧的第一输出线和第二输出线，以分别获得第一和第二电位; 操作单元，其计算所述第一和第二电位之间的第一差分值; 处理单元，对所述第一差分值进行运算; 第二获取单元，其获取外部设备的参考电位侧的第一输入线的第三电位; 以及输出单元，其通过将第二差分值叠加在第三电位上来生成劣化信号。

公开(公告)号：US20090044188A1

公开(公告)日：2009-02-12

申请号：US12247509

申请日：2008-10-08

申请人： Tatsunori KANAI ,  Seiji MAEDA ,  Hirokuni YANO ,  Kenichiro YOSHII

发明人： Tatsunori KANAI ,  Seiji MAEDA ,  Hirokuni YANO ,  Kenichiro YOSHII

IPC分类号： G06F9/46

CPC分类号： G06F9/4887 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

摘要： An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.

摘要翻译： 信息处理系统以特定的时间间隔周期性地执行实时操作。 该系统包括用于执行调度操作的单元，该调度操作将实时操作分配给处理器，以由处理器以特定时间间隔周期性地执行实时操作，用于计算实际的执行时间的比率的单元 基于具体的时间间隔和关于处理器以第一操作速度进行实时操作所需的时间的成本信息，处理器以第一操作速度执行的时间操作，以及用于执行 操作速度控制操作以在低于第一操作速度的第二操作速度下操作处理器，基于所计算的比率来确定第二操作速度。

公开(公告)号：US20090019266A1

公开(公告)日：2009-01-15

申请号：US12037357

申请日：2008-02-26

申请人： Seiji MAEDA

发明人： Seiji MAEDA

IPC分类号： G06F12/08 ,  G06F9/44

CPC分类号： G06F9/45516 ,  G06F9/30047 ,  G06F9/383

摘要： With respect to memory access instructions contained in an internal representation program, an information processing apparatus generates a load cache instruction, a cache hit judgment instruction, and a cache miss instruction that is executed in correspondence with a result of a judgment process performed according to the cache hit judgment instruction. In a case where the internal representation program contains a plurality of memory access instructions having a possibility of causing accesses to mutually the same cache line in a cache memory, the information processing apparatus generates a combine instruction instructing that judgment results of the judgment processes that are performed according to the cache hit judgment instruction should be combined into one judgment result. The information processing apparatus outputs an output program that contains these instructions that have been generated.

摘要翻译： 关于包含在内部表示程序中的存储器访问指令，信息处理装置生成与根据所述内部表示程序执行的判断处理的结果相对应地执行的加载高速缓存指令，高速缓存命中判定指令和高速缓存未命中指令 缓存命中判断指令。 在内部表示程序包含多个具有访问高速缓存存储器中的相同高速缓存行的可能性的存储器访问指令的情况下，信息处理设备产生组合指令，指示判断过程的判断结果为 根据缓存命中判断指令执行的操作应合并为一个判断结果。 信息处理装置输出包含已经生成的这些指令的输出程序。

公开(公告)号：US20080256296A1

公开(公告)日：2008-10-16

申请号：US12035977

申请日：2008-02-22

申请人： Seiji MAEDA

发明人： Seiji MAEDA

IPC分类号： G06F12/00

CPC分类号： G06F12/0893

摘要： A processor is provided with a register and operates to: determine whether a first tag address match with a second tag address, the first tag address being derived from a target main memory address that is to be accessed for obtaining target data subjected to a computation, the second tag address being one of the tag addresses stored in the local memory; start copying data stored in at least one of the cache lines assigned with a line number that matches with a target line number that is derived from the target main memory address into the register before completing the determination of match between the first tag address and the second tag address; and access the register to obtain the data copied from the local memory when determined that the first tag address match with the second tag address.

摘要翻译： 处理器设置有寄存器，用于：确定第一标签地址是否与第二标签地址匹配，所述第一标签地址是从要被访问的目标主存储器地址导出以获得经过计算的目标数据， 第二标签地址是存储在本地存储器中的标签地址之一; 在完成第一标签地址和第二标签地址之间的匹配确定之前，开始将分配有与从目标主存储器地址导出的目标行号相匹配的行号的高速缓存行中存储的数据复制到寄存器中 标签地址 并且当确定第一标签地址与第二标签地址匹配时，访问该寄存器以获得从本地存储器复制的数据。