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    METHOD AND SYSTEM FOR PERFORMING REAL-TIME OPERATION
    1.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING REAL-TIME OPERATION 有权
    执行实时操作的方法和系统

    公开(公告)号：US20090044188A1

    公开(公告)日：2009-02-12

    申请号：US12247509

    申请日：2008-10-08

    申请人： Tatsunori KANAI ,  Seiji MAEDA ,  Hirokuni YANO ,  Kenichiro YOSHII

    发明人： Tatsunori KANAI ,  Seiji MAEDA ,  Hirokuni YANO ,  Kenichiro YOSHII

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4887 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24

    摘要： An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.

    摘要翻译： 信息处理系统以特定的时间间隔周期性地执行实时操作。 该系统包括用于执行调度操作的单元，该调度操作将实时操作分配给处理器，以由处理器以特定时间间隔周期性地执行实时操作，用于计算实际的执行时间的比率的单元 基于具体的时间间隔和关于处理器以第一操作速度进行实时操作所需的时间的成本信息，处理器以第一操作速度执行的时间操作，以及用于执行 操作速度控制操作以在低于第一操作速度的第二操作速度下操作处理器，基于所计算的比率来确定第二操作速度。

    SEMICONDUCTOR STORAGE DEVICE
    3.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权
    半导体存储设备

    公开(公告)号：US20120221776A1

    公开(公告)日：2012-08-30

    申请号：US13462905

    申请日：2012-05-03

    申请人： Eiji YOSHIHASHI ,  Hirokuni YANO ,  Shinji YONEZAWA

    发明人： Eiji YOSHIHASHI ,  Hirokuni YANO ,  Shinji YONEZAWA

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0804 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7205

    摘要： According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released.

    摘要翻译： 根据实施例，由修剪请求指定的第一存储区域和第二存储区域由第一管理单元管理，并且由修剪请求指定的第二存储区域由第二管理单元管理。 其中第一管理单元的数据全部由来自第一或第二存储区域的修剪请求指定的块和第二管理单元的数据全部由来自第二存储区域的修剪请求指定的块被释放。

    MEMORY SYSTEM AND CONTROLLER
    4.
    发明申请
    MEMORY SYSTEM AND CONTROLLER 有权
    存储系统和控制器

    公开(公告)号：US20100169549A1

    公开(公告)日：2010-07-01

    申请号：US12542222

    申请日：2009-08-17

    申请人： Hirokuni YANO ,  Naoki Otsuka

    发明人： Hirokuni YANO ,  Naoki Otsuka

    IPC分类号： G06F12/00 ,  G06F17/30 ,  G06F12/08

    CPC分类号： G06F12/0862 ,  G06F12/0868 ,  G06F2212/214 ,  G06F2212/222 ,  G06F2212/6028

    摘要： A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit.

    摘要翻译： A控制器在从主机设备的读取请求中指定的数据范围内设置遵循该数据范围的顶部部分的第一数据范围的预定大小和在该数据范围之后的第二数据范围的预定大小 第一数据范围，并且在从具有比执行数据的读/写数据的第一存储单元的数据输出延迟更小的第二存储单元或第三存储单元传送对应于第一数据范围的数据的主机设备之后 控制器在第二存储单元或第三存储单元中搜索对应于第二数据范围的数据。

    METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请
    METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE 有权
    控制半导体存储器件的方法

    公开(公告)号：US20120239992A1

    公开(公告)日：2012-09-20

    申请号：US13486718

    申请日：2012-06-01

    申请人： Toshikatsu HIDA ,  Shinichi KANNO ,  Hirokuni YANO ,  Kazuya KITSUNAI ,  Shigehiro ASANO ,  Junji YANO

    发明人： Toshikatsu HIDA ,  Shinichi KANNO ,  Hirokuni YANO ,  Kazuya KITSUNAI ,  Shigehiro ASANO ,  Junji YANO

    IPC分类号： G11C29/00 ,  G06F11/16

    CPC分类号： G06F11/1412 ,  G06F11/1068 ,  G06F11/1402 ,  G06F12/02 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431

    摘要： A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.

    摘要翻译： 一种控制包括多个块的非易失性半导体存储器的方法，所述多个块中的每一个是数据擦除单元，包括：基于预定条件，将所监视的块作为所述多个块中的刷新操作的候补确定 。 该方法包括监视存储在所监视的块中的数据的错误计数，并且不监视存储在多个块中的被监视块之外的块中存储的数据的错误计数。 该方法还包括对存储在监视块中的数据执行刷新操作，其中错误计数大于第一阈值。

    MEMORY SYSTEM AND DATA TRANSFER METHOD
    6.
    发明申请
    MEMORY SYSTEM AND DATA TRANSFER METHOD 审中-公开
    存储系统和数据传输方法

    公开(公告)号：US20120159050A1

    公开(公告)日：2012-06-21

    申请号：US13328471

    申请日：2011-12-16

    申请人： Hirokuni YANO ,  Eiji Yoshihashi

    发明人： Hirokuni YANO ,  Eiji Yoshihashi

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F13/1668 ,  G06F12/0246

    摘要： According to one embodiment, a memory system comprises a nonvolatile memory including a memory cell array and a read buffer and a controller configured to receive a read request and to issue a first read command and a second read command to the memory. When issuing the first read command, the memory transfers data of the first size from the memory cell array to the read buffer and outputs the data from the read buffer to the controller. When issuing the second read command, the memory transfers first data of the first size from the memory cell array to the read buffer, outputs the first data from the read buffer to the controller, and transfers second data of the first size from the memory cell array to the read buffer. The controller selects one command from the two commands according to the read request.

    摘要翻译： 根据一个实施例，存储器系统包括非易失性存储器，其包括存储单元阵列和读取缓冲器以及被配置为接收读取请求并向存储器发出第一读取命令和第二读取命令的控制器。 当发出第一读命令时，存储器将第一大小的数据从存储单元阵列传送到读缓冲器，并将数据从读缓冲器输出到控制器。 当发出第二读命令时，存储器将第一大小的第一数据从存储单元阵列传送到读缓冲器，将第一数据从读缓冲器输出到控制器，并从存储单元传送第一大小的第二数据 数组到读缓冲区。 控制器根据读取请求从两个命令中选择一个命令。

    MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM, CONTROLLER, AND METHOD OF CONTROLLING MEMORY SYSTEM 有权
    存储器系统，控制器和控制存储器系统的方法

    公开(公告)号：US20100169553A1

    公开(公告)日：2010-07-01

    申请号：US12566236

    申请日：2009-09-24

    申请人： Hirokuni YANO ,  Shinichi Kanno

    发明人： Hirokuni YANO ,  Shinichi Kanno

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/7202

    摘要： A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.

    摘要翻译： 根据本发明的实施例的存储器系统包括易失性第一存储单元，非易失性第二存储单元，经由第一存储单元在主机设备和第二存储单元之间传送数据的控制器。 存储系统监视从第一存储单元中的主机设备写入的数据是否具有管理单元中的特定模式。 当要刷新到第二存储单元的数据具有特定模式时，存储器系统将不在第二存储单元中使用的无效地址值设置为数据。

    MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM
    9.
    发明申请
    MEMORY SYSTEM AND CONTROL METHOD OF MEMORY SYSTEM 有权
    存储系统的存储系统和控制方法

    公开(公告)号：US20130232296A1

    公开(公告)日：2013-09-05

    申请号：US13599087

    申请日：2012-08-30

    申请人： Shinji YONEZAWA ,  Takashi HIRAO ,  Hirokuni YANO ,  Mitsunori TADOKORO ,  Hiroki MATSUDAIRA ,  Akira SAWAOKA

    发明人： Shinji YONEZAWA ,  Takashi HIRAO ,  Hirokuni YANO ,  Mitsunori TADOKORO ,  Hiroki MATSUDAIRA ,  Akira SAWAOKA

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G11C2211/5641

    摘要： A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.

    摘要翻译： 实施例中的存储器系统包括存储用户数据的非易失性半导体存储器，正向查找地址转换表和反向查找地址转换表以及控制器。 控制器被配置为基于这两个表来确定存储在非易失性半导体存储器中的用户数据有效或无效。 控制器可以执行数据组织，选择确定有效的数据并在新的块中重写数据。 控制器可以以预定的比例交替地对新的块执行写入处理和重写处理。 当条件满足时，控制器可以基于写入请求中包括的地址和写入数据来确定是否满足预定条件，并且当条件不满足时将控制器写入SLC模式中的数据。