-
公开(公告)号：US06452251B1
公开(公告)日：2002-09-17
申请号：US09540737
申请日：2000-03-31
IPC分类号： H01L2900
CPC分类号： H01L23/5223 , H01L21/76877 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.
摘要翻译： 制造在具有将电容器的底板（41B，111A）互连到芯片电路中的带接触（41A，119A）的半导体芯片上制造的电容器（60和126）。 在一个版本中，构成电容器底板的材料的延伸形成带接触。 在另一版本中，电容器（185）包括底板，电介质层和顶板的折叠，以利用可用空间并因此增加其电容。 几种制造方法允许将各种形式的电容器的制造集成到标准的双重或单个镶嵌制造工艺中，包括铜镶嵌工艺。
-
公开(公告)号：US06548338B2
公开(公告)日：2003-04-15
申请号：US09764504
申请日：2001-01-17
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译： 一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。 因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。
-
公开(公告)号：US06236103B1
公开(公告)日：2001-05-22
申请号：US09283828
申请日：1999-03-31
申请人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
发明人： Kerry Bernstein , Robert M. Geffken , Wilbur D. Pricer , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/3672 , H01L23/3735 , H01L27/0805 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.
摘要翻译： 一种显着且非常有效的去耦电容器和散热器组合，其在单个结构中提供散热器和去耦电容器，其紧邻芯片上的有源电路，需要散热或去耦电容或两者兼有。 这通过在其中具有掩埋氧化物层的半导体芯片上形成集成的高性能去耦电容器来实现，所述高性能去耦电容器使用形成在芯片的背面上并且电连接到有源芯片电路的大于30微米厚的金属沉积物 导致显着且非常有效的去耦电容器和散热器紧邻芯片上的有源电路，需要这种去耦电容和散热能力。 去耦电容可以使用芯片本身的衬底作为电容板之一，并且形成金属沉积物作为第二电容板，其也用作形成在芯片中的有源电路的散热器。 因此，该结构提供了重要且有效的去耦电容，其紧邻芯片上的有源电路，需要这种去耦电容，并为解耦的有源电路提供改进的散热。
-
公开(公告)号：US20080203579A1
公开(公告)日：2008-08-28
申请号：US12116490
申请日：2008-05-07
IPC分类号： H01L23/522
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译： 用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨 在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层 还包含氧化物和聚亚芳基。 沉积步骤防止层压的绝缘体叠层溅射到通孔中。 此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。
-
公开(公告)号：US07381637B2
公开(公告)日：2008-06-03
申请号：US11053706
申请日：2005-02-08
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
公开(公告)号：US07655547B2
公开(公告)日：2010-02-02
申请号：US12062612
申请日：2008-04-04
IPC分类号： H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
公开(公告)号：US06939791B2
公开(公告)日：2005-09-06
申请号：US10632653
申请日：2003-08-02
IPC分类号： H01L21/288 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs. Portions of the metallic capping layer between the damascene conductive wires/studs are removed to form a metallic cap on each damascene conductive wire/stud and to conductively isolate one or more of the damascene conductive wires/studs. A portion of the metallic capping layer may be removed from a particular damascene conductive wire/stud such that no metallic capping material remains conductively coupled to the particular damascene conductive wire/stud. A second insulative layer is formed on the first insulative layer such that the second insulative layer covers the metallic caps. Damascene conductive wiring lines are formed within the second insulative layer above the metallic caps and are conductively coupled to the metallic caps.
摘要翻译： 用于在镶嵌导电线/螺柱和镶嵌导电布线结构之间形成金属封盖界面的方法和结构。 该方法在衬底层上形成第一绝缘层，随后在第一绝缘层中形成镶嵌导电线/螺柱。 每个镶嵌导电线/螺柱的下部与衬底层内的电子器件（例如，场效应晶体管）或浅沟槽隔离层接触。 去除第一绝缘层的顶部，例如通过蚀刻，使得镶嵌导电线/螺柱的上部保持在第一绝缘层上方。 金属盖层形成在镶嵌导电线/螺柱的上部，使得金属覆盖层与镶嵌导电线/螺柱导电接触。 去除镶嵌导电线/螺柱之间的金属覆盖层的部分，以在每个镶嵌导电线/柱上形成金属盖，并导电隔离一个或多个镶嵌导电线/螺柱。 金属覆盖层的一部分可以从特定的镶嵌导电线/螺柱移除，使得没有金属封盖材料保持与特定的镶嵌导电线/螺柱导电耦合。 第二绝缘层形成在第一绝缘层上，使得第二绝缘层覆盖金属盖。 大马士革导电布线形成在金属盖上方的第二绝缘层内，并与金属盖导电耦合。
-
公开(公告)号：US06498385B1
公开(公告)日：2002-12-24
申请号：US09388314
申请日：1999-09-01
申请人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
发明人： Timothy H. Daubenspeck , Daniel C. Edelstein , Robert M. Geffken , William T. Motsiff , Anthony K. Stamper , Steven H. Voldman
IPC分类号： H01L2900
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76843 , H01L23/5258 , H01L28/20 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method of fabricating a semiconductor corrosion resistant metal fuse line including a refractory liner which can also act as a resistor is disclosed. Fabrication is accomplished using damascene process. The metal structure can be formed on a semiconductor substrate including a first portion including a first layer and a second layer, the first layer having higher resistivity than the second layer, the second layer having horizontal and vertical surfaces that are in contact with the first layer in the first portion, and a second portion coupled to the first portion, the second portion being comprised of the first layer, the first layer not being in contact with the horizontal and vertical surfaces of the second layer in the second portion. The metal structure can be used as a corrosion resistant fuse. The metal structure can also be used as a resistive element. The high voltage tolerant resistor structure allows for usage in mixed-voltage, and mixed signal and analog/digital applications. The resistor element has low capacitance, low skin effect, high linearity, a high melting temperature, and a high critical current to failure. The resistor structure can be formed on the walls of a dielectric trough. The structure can be applied to circuit applications such as an ESD network, an RC-coupled MOSFET, a resistor ballasted MOSFET and others. The resistors can be in series with the MOSFET or other structures.
摘要翻译： 公开了一种制造半导体耐腐蚀金属熔丝线的结构和方法，其包括也可以用作电阻器的耐火衬垫。 使用镶嵌工艺完成制作。 金属结构可以形成在包括包括第一层和第二层的第一部分的半导体衬底上，第一层具有比第二层更高的电阻率，第二层具有与第一层接触的水平和垂直表面 在第一部分中，以及第二部分，其联接到第一部分，第二部分由第一层组成，第一层不与第二部分中的第二层的水平和垂直表面接触。 金属结构可用作耐腐蚀保险丝。 金属结构也可以用作电阻元件。高耐压电阻器结构允许在混合电压，混合信号和模拟/数字应用中使用。 电阻元件具有低电容，低效果，高线性度，高熔点温度和高临界电流故障。 电阻器结构可以形成在电介质槽的壁上。 该结构可以应用于诸如ESD网络，RC耦合MOSFET，电阻器镇流MOSFET等电路应用。 电阻可以与MOSFET或其他结构串联。
-
公开(公告)号：US06426249B1
公开(公告)日：2002-07-30
申请号：US09526354
申请日：2000-03-16
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L21/76807 , H01L21/76831 , H01L21/76897 , H01L23/5223
摘要： A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metalization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.
摘要翻译： 在晶圆的BEOL中形成作为金属双镶嵌工艺的一部分的金属电容器。 电容器的下板（27）夹在绝缘层（25）和电介质层（29）之间。 相反侧的绝缘层邻接金属化层（23,24），电介质层将电容器的下板与电容器的上板（59）分开。 下板的一部分（27A）突出成与铜（63）相邻的通孔（37）。 通孔与上板突出到共同的表面，但是由上板电隔离。 通孔也延伸到金属化层。
-
公开(公告)号：US20080293242A1
公开(公告)日：2008-11-27
申请号：US12062612
申请日：2008-04-04
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
-
-
-
-
-
-
-
-
搜索结果
394 条记录 (耗时 0.082 秒)