-
公开(公告)号：US06939791B2
公开(公告)日：2005-09-06
申请号：US10632653
申请日：2003-08-02
IPC分类号： H01L21/288 , H01L21/768 , H01L21/4763 , H01L21/44
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs. Portions of the metallic capping layer between the damascene conductive wires/studs are removed to form a metallic cap on each damascene conductive wire/stud and to conductively isolate one or more of the damascene conductive wires/studs. A portion of the metallic capping layer may be removed from a particular damascene conductive wire/stud such that no metallic capping material remains conductively coupled to the particular damascene conductive wire/stud. A second insulative layer is formed on the first insulative layer such that the second insulative layer covers the metallic caps. Damascene conductive wiring lines are formed within the second insulative layer above the metallic caps and are conductively coupled to the metallic caps.
摘要翻译： 用于在镶嵌导电线/螺柱和镶嵌导电布线结构之间形成金属封盖界面的方法和结构。 该方法在衬底层上形成第一绝缘层，随后在第一绝缘层中形成镶嵌导电线/螺柱。 每个镶嵌导电线/螺柱的下部与衬底层内的电子器件（例如，场效应晶体管）或浅沟槽隔离层接触。 去除第一绝缘层的顶部，例如通过蚀刻，使得镶嵌导电线/螺柱的上部保持在第一绝缘层上方。 金属盖层形成在镶嵌导电线/螺柱的上部，使得金属覆盖层与镶嵌导电线/螺柱导电接触。 去除镶嵌导电线/螺柱之间的金属覆盖层的部分，以在每个镶嵌导电线/柱上形成金属盖，并导电隔离一个或多个镶嵌导电线/螺柱。 金属覆盖层的一部分可以从特定的镶嵌导电线/螺柱移除，使得没有金属封盖材料保持与特定的镶嵌导电线/螺柱导电耦合。 第二绝缘层形成在第一绝缘层上，使得第二绝缘层覆盖金属盖。 大马士革导电布线形成在金属盖上方的第二绝缘层内，并与金属盖导电耦合。
-
公开(公告)号：US06680514B1
公开(公告)日：2004-01-20
申请号：US09745047
申请日：2000-12-20
IPC分类号： H01L2976
CPC分类号： H01L21/76885 , H01L21/2885 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for forming a metallic capping interface between damascene conductive wires/studs and damascene conductive wiring line structures. The method forms a first insulative layer on a substrate layer, followed by forming damascene conductive wires/studs in the first insulative layer. A lower portion of each damascene conductive wire/stud is in contact with an electronic device (e.g., a field effect transistor), or a shallow trench isolation, that is within the substrate layer. A top portion of the first insulative layer is removed, such as by etching, such that an upper portion of the damascene conductive wires/studs remain above the first insulative layer. A metallic capping layer is formed on the upper portions of the damascene conductive wires/studs such that the metallic capping layer is in conductive contact with the damascene conductive wires/studs. Portions of the metallic capping layer between the damascene conductive wires/studs are removed to form a metallic cap on each damascene conductive wire/stud and to conductively isolate one or more of the damascene conductive wires/studs. A portion of the metallic capping layer may be removed from a particular damascene conductive wire/stud such that no metallic capping material remains conductively coupled to the particular damascene conductive wire/stud. A second insulative layer is formed on the first insulative layer such that the second insulative layer covers the metallic caps. Damascene conductive wiring lines are formed within the second insulative layer above the metallic caps and are conductively coupled to the metallic caps.
摘要翻译： 用于在镶嵌导电线/螺柱和镶嵌导电布线结构之间形成金属封盖界面的方法和结构。 该方法在衬底层上形成第一绝缘层，随后在第一绝缘层中形成镶嵌导电线/螺柱。 每个镶嵌导电线/螺柱的下部与衬底层内的电子器件（例如，场效应晶体管）或浅沟槽隔离层接触。 去除第一绝缘层的顶部，例如通过蚀刻，使得镶嵌导电线/螺柱的上部保持在第一绝缘层上方。 金属盖层形成在镶嵌导电线/螺柱的上部，使得金属覆盖层与镶嵌导电线/螺柱导电接触。 去除镶嵌导电线/螺柱之间的金属覆盖层的部分，以在每个镶嵌导电线/柱上形成金属盖，并导电隔离一个或多个镶嵌导电线/螺柱。 金属覆盖层的一部分可以从特定的镶嵌导电线/螺柱移除，使得没有金属封盖材料保持与特定的镶嵌导电线/螺柱导电耦合。 第二绝缘层形成在第一绝缘层上，使得第二绝缘层覆盖金属盖。 大马士革导电布线形成在金属盖上方的第二绝缘层内，并与金属盖导电耦合。
-
公开(公告)号：US06426558B1
公开(公告)日：2002-07-30
申请号：US09854890
申请日：2001-05-14
申请人： Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
发明人： Jonathan Chapple-Sokol , Paul M. Feeney , Robert M. Geffken , David V. Horak , Mark P. Murray , Anthony K. Stamper
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L21/76807 , H01L21/76849 , H01L21/76883 , H01L21/76885 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is described which improves the manufacturability of integrated circuit interconnect and stud contacts in contact with semiconductor substrates and upper levels of metallization. The monolithic structure is formed from a thick layer of refractory metal. A variation in the monolithic structure is in the use of a dual damascene local interconnect portion of the structure which allows the local interconnect to pass over structures previously formed on the substrate.
摘要翻译： 描述了一种方法和结构，其改进了与半导体衬底接触的集成电路互连和螺柱触头的可制造性以及较高级别的金属化。 整体结构由难熔金属的厚层形成。 整体结构的变化是使用结构的双镶嵌局部互连部分，其允许局部互连通过先前形成在衬底上的结构。
-
公开(公告)号：US06653737B2
公开(公告)日：2003-11-25
申请号：US10159181
申请日：2002-05-31
IPC分类号： H01L214763
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76814 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).
-
公开(公告)号：US06436814B1
公开(公告)日：2002-08-20
申请号：US09718010
申请日：2000-11-21
IPC分类号： H01L214763
CPC分类号： H01L21/76847 , H01L21/76805 , H01L21/76814 , H01L21/76877 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).
-
公开(公告)号：US06503827B1
公开(公告)日：2003-01-07
申请号：US09605806
申请日：2000-06-28
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/76834 , H01L21/7684
摘要： A method of reducing the planarization defects produced during the manufacture of semiconductor devices. A sacrificial layer, having defects produced during a interconnection feature planarization step, is removed prior to the formation of subsequent layers to reduce the replication of unwanted defects.
摘要翻译： 一种减少在制造半导体器件期间产生的平坦化缺陷的方法。 在互连特征平面化步骤之间产生的缺陷的牺牲层在形成后续层之前被去除以减少不想要的缺陷的复制。
-
公开(公告)号：US09054156B2
公开(公告)日：2015-06-09
申请号：US13561133
申请日：2012-07-30
申请人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
发明人： Chiahsun Tseng , David V. Horak , Chun-chen Yeh , Yunpeng Yin
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/768 , H01L21/02244 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76816 , H01L23/498 , H01L29/0692 , H01L45/1691 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.
摘要翻译： 金属层沉积在材料层上。 金属层包括可通过等离子体氧化或氮化转化为含介电金属的化合物的元素金属。 在金属层上形成硬掩模部分。 在硬掩模部分的至少一个第一侧壁上形成等离子体不可渗透的间隔物，同时硬掩模部分的至少一个第二侧壁物理暴露。 进行等离子体氧化或氮化以将金属层的物理暴露表面转化为含介电金属的化合物。 重复将硬掩模部分的表面拉回序列，腔蚀刻，另一表面拉回和将顶表面转化为含介电金属的化合物，以形成具有不受光刻最小值限制的间隔的孔图案 尺寸。
-
公开(公告)号：US08946866B2
公开(公告)日：2015-02-03
申请号：US13490239
申请日：2012-06-06
申请人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
发明人： Charles W. Koburger, III , Steven J. Holmes , David V. Horak , Kurt R. Kimmel , Karen E. Petrillo , Christopher F. Robinson
CPC分类号： G03F7/70691 , G03F7/70341 , G03F7/70808
摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.
摘要翻译： 提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。 这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。 前表面是物品的主要表面。 具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。 以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦， 周缘连接到内边缘。
-
公开(公告)号：US08853076B2
公开(公告)日：2014-10-07
申请号：US13607856
申请日：2012-09-10
IPC分类号： H01L21/44
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译： 本文公开了金属栅极结构中的自对准触点和制造方法。 该方法包括形成具有侧壁结构的金属栅极结构。 该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。 该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。
-
10.发明授权公开(公告)号：US08772168B2
公开(公告)日：2014-07-08
申请号：US13353708
申请日：2012-01-19
IPC分类号： H01L21/311
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译： 通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。 实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属， 平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。 实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。
-
-
-
-
-
-
-
-
-
搜索结果
340 条记录 (耗时 0.026 秒)