-
公开(公告)号：US07655547B2
公开(公告)日：2010-02-02
申请号：US12062612
申请日：2008-04-04
IPC分类号： H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
公开(公告)号：US07393777B2
公开(公告)日：2008-07-01
申请号：US10984439
申请日：2004-11-09
IPC分类号： H01L21/4763 , H01L21/311
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译： 用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨 在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层 还包含氧化物和聚亚芳基。 沉积步骤防止层压的绝缘体叠层溅射到通孔中。 此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。
-
公开(公告)号：US06846741B2
公开(公告)日：2005-01-25
申请号：US10202134
申请日：2002-07-24
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76811 , H01L21/76813
摘要： A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.
摘要翻译： 用于双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上方形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽，从而产生牺牲钨 在槽中的侧壁间隔物，图案化叠层绝缘体堆叠，去除牺牲侧壁间隔物，在图案化的层压绝缘体堆叠中形成通孔，以及将金属衬垫和导电材料沉积到通孔和槽中，其中层压绝缘体堆叠包括介电层 还包含氧化物和聚亚芳基。 沉积步骤防止层压的绝缘体叠层溅射到通孔中。 此外，沉积步骤包括清洁通孔和槽，可选地执行反应离子蚀刻或氩溅射清洗，在通孔和槽上沉积多个金属层，以及在通孔和槽中沉积铜。
-
公开(公告)号：US06674168B1
公开(公告)日：2004-01-06
申请号：US10248452
申请日：2003-01-21
申请人： Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人： Edward C. Cooney, III , Robert M Geffken , Vincent J McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号： H01L2100
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译： 一种重新加工BEOL（处理线的后端）金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部 介电常数材料比第二介电层。
-
公开(公告)号：US20080293242A1
公开(公告)日：2008-11-27
申请号：US12062612
申请日：2008-04-04
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
公开(公告)号：US06982227B2
公开(公告)日：2006-01-03
申请号：US10687294
申请日：2003-10-16
申请人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
发明人： Edward C. Cooney, III , Robert M. Geffken , Vincent J. McGahay , William T. Motsiff , Mark P. Murray , Amanda L. Piper , Anthony K. Stamper , David C. Thomas , Christy S. Tyberg , Elizabeth T. Webster
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76807 , H01L21/76892 , H01L23/525 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.
摘要翻译： 一种重新加工BEOL（处理线的后端）金刚石冶金的金属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部 介电常数材料比第二介电层。
-
公开(公告)号：US07381637B2
公开(公告)日：2008-06-03
申请号：US11053706
申请日：2005-02-08
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76808 , H01L21/76811 , H01L21/76865
摘要： A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.
摘要翻译： 用于单镶嵌或双镶嵌互连结构的方法和结构包括在衬底上的金属化层中形成布线，在金属化层上形成叠层绝缘体堆叠，在叠层绝缘体堆叠上形成硬掩模，在硬掩模中形成槽， 层叠绝缘体堆叠，在图案化的层叠绝缘体堆叠中形成通路，在通孔的底部产生侧壁间隔物，在侧壁间隔物上沉积抗反射涂层，蚀刻槽，去除抗反射涂层，沉积金属 槽，通路和侧壁间隔物中的层，以及在槽和通孔中施加导电材料。 层压绝缘体堆叠包括还包含氧化物和聚亚芳基的电介质层。
-
8.发明授权Vertical integrated circuit switches, design structure and methods of fabricating same 有权垂直集成电路开关，设计结构及其制造方法公开(公告)号：US08604898B2
公开(公告)日：2013-12-10
申请号：US12426561
申请日：2009-04-20
IPC分类号： H01H51/22
CPC分类号： H01H59/0009 , H01L2924/0002 , H01L2924/00
摘要： Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.
摘要翻译： 本文提供垂直集成MEMS开关，制造这种垂直开关的设计结构和方法。 制造MEMS开关的方法包括在晶片中形成至少两个垂直延伸的通孔，并用金属填充至少两个垂直延伸的通孔以形成至少两个垂直延伸的导线。 该方法还包括从底侧打开晶片中的空隙，使得垂直延伸的线中的至少一个可在空隙内移动。
-
9.发明授权Device and methodology for reducing effective dielectric constant in semiconductor devices 有权用于降低半导体器件中有效介电常数的器件和方法公开(公告)号：US07892940B2
公开(公告)日：2011-02-22
申请号：US11851123
申请日：2007-09-06
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。
-
10.发明授权Device and methodology for reducing effective dielectric constant in semiconductor devices 有权用于降低半导体器件中有效介电常数的器件和方法公开(公告)号：US08343868B2
公开(公告)日：2013-01-01
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。
-
-
-
-
-
-
-
-
-
搜索结果
58 条记录 (耗时 0.027 秒)