公开(公告)号：US06452251B1

公开(公告)日：2002-09-17

申请号：US09540737

申请日：2000-03-31

申请人： Kerry Bernstein ,  Robert M. Geffken ,  Anthony K. Stamper ,  Stephen A. St. Onge

发明人： Kerry Bernstein ,  Robert M. Geffken ,  Anthony K. Stamper ,  Stephen A. St. Onge

IPC分类号： H01L2900

CPC分类号： H01L23/5223 ,  H01L21/76877 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor (60 and 126) fabricated on a semiconductor chip which has a strap contact (41A, 119A) which interconnects the bottom plate (41B, 111A) of the capacitor into the chip circuitry. In one version, an extension of the material making up the bottom plate of the capacitor forms the strap contact. In another version, the capacitor (185) includes a folding of the bottom plate, dielectric layer and top plate to utilize available space and thus increase its capacitance. Several manufacturing methods allow for integration of fabrication of the various versions of the capacitor into a standard dual or single damascene manufacturing process, including a copper damascene process.

摘要翻译： 制造在具有将电容器的底板（41B，111A）互连到芯片电路中的带接触（41A，119A）的半导体芯片上制造的电容器（60和126）。 在一个版本中，构成电容器底板的材料的延伸形成带接触。 在另一版本中，电容器（185）包括底板，电介质层和顶板的折叠，以利用可用空间并因此增加其电容。 几种制造方法允许将各种形式的电容器的制造集成到标准的双重或单个镶嵌制造工艺中，包括铜镶嵌工艺。

公开(公告)号：US07002221B2

公开(公告)日：2006-02-21

申请号：US10604988

申请日：2003-08-29

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L23/62

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

公开(公告)号：US08466501B2

公开(公告)日：2013-06-18

申请号：US12784583

申请日：2010-05-21

申请人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

发明人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

IPC分类号： H01L29/808

CPC分类号： G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/8086

摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).

摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。

公开(公告)号：US07868423B2

公开(公告)日：2011-01-11

申请号：US12269073

申请日：2008-11-12

申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

IPC分类号： H01L21/02

CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

公开(公告)号：US07253096B2

公开(公告)日：2007-08-07

申请号：US11289915

申请日：2005-11-30

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L21/4763

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US07701015B2

公开(公告)日：2010-04-20

申请号：US10596573

申请日：2003-12-16

申请人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

发明人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

IPC分类号： H01L29/72

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

摘要翻译： 公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。 垂直双极晶体管比CMOS晶体管更高的器件。 在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。 布线层位于钝化层的上方。 垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

公开(公告)号：US07317240B2

公开(公告)日：2008-01-08

申请号：US11303118

申请日：2005-12-16

申请人： Michael D. Hulvey ,  Stephen A. St. Onge

发明人： Michael D. Hulvey ,  Stephen A. St. Onge

IPC分类号： H01L27/102

CPC分类号： H01L23/522 ,  H01L23/485 ,  H01L27/0744 ,  H01L27/082 ,  H01L29/41708 ,  H01L29/42304 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device. The device includes two bipolar transistors electrically connected to each other. Each bipolar transistor of the two bipolar transistors may include a base contact and an emitter contact surrounding the base contact, wherein the emitters contacts of the two bipolar transistor are in electrical contact with each other. A first bipolar transistor of the two bipolar transistors may have a first wiring stack and a second bipolar transistor two bipolar transistors may have a second wiring stack, wherein the second wiring stack includes at least one more wiring level than the first wiring stack.

摘要翻译： 一个装置。 该器件包括彼此电连接的两个双极晶体管。 两个双极晶体管的每个双极晶体管可以包括基极触点和围绕基极触点的发射极触点，其中两个双极晶体管的发射极触点彼此电接触。 两个双极晶体管的第一双极晶体管可以具有第一布线堆叠和第二双极晶体管两个双极晶体管可以具有第二布线堆叠，其中第二布线堆叠包括比第一布线堆叠更多的布线层。

公开(公告)号：US06998699B2

公开(公告)日：2006-02-14

申请号：US10645282

申请日：2003-08-21

申请人： Michael D. Hulvey ,  Stephen A. St. Onge

发明人： Michael D. Hulvey ,  Stephen A. St. Onge

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC分类号： H01L23/522 ,  H01L23/485 ,  H01L27/0744 ,  H01L27/082 ,  H01L29/41708 ,  H01L29/42304 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bipolar transistor having a base contact surrounded by an emitter contact. A plurality of wires extending from the base contact and the emitter contact of the bipolar transistor, wherein the wires of the base contact are stacked higher than the wires of the emitter contact. A device comprising a plurality of these bipolar transistors, wherein at least one side of each emitter contact abuts each adjacent transistor. Increasing the wiring stack of each row of transistors in the device as the distance between the row and the current input increases.

摘要翻译： 具有由发射极接触包围的基极接触的双极晶体管。 从双极晶体管的基极触点和发射极触点延伸的多根导线，其中基极触点的导线堆叠高于发射极触点的导线。 一种包括多个这些双极晶体管的器件，其中每个发射极接触点的至少一侧邻接每个相邻的晶体管。 当行和当前输入之间的距离增加时，增加器件中每行晶体管的布线堆叠。

公开(公告)号：US06448124B1

公开(公告)日：2002-09-10

申请号：US09439067

申请日：1999-11-12

申请人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

发明人： Douglas D. Coolbaugh ,  James S. Dunn ,  Peter J. Geiss ,  Peter B. Gray ,  David L. Harame ,  Kathryn T. Schonenberg ,  Stephen A. St. Onge ,  Seshadri Subbanna

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/763 ,  H01L21/8249

摘要： A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

摘要翻译： 提供一种形成BiCMOS集成电路的方法，其包括以下步骤：（a）在衬底的第一区域中形成双极器件的第一部分; （b）在所述第一区域上形成第一保护层以保护所述双极器件的所述第一部分; （c）在所述衬底的第二区域中形成场效应晶体管器件; （d）在所述衬底的所述第二区域上形成第二保护层以保护所述场效应晶体管器件; （e）去除所述第一保护层; （f）在所述衬底的所述第一区域中形成所述双极器件的第二部分; 和（g）去除所述第二保护层。

公开(公告)号：US20140033149A1

公开(公告)日：2014-01-30

申请号：US13561760

申请日：2012-07-30

申请人： Robert A. Groves ,  Wan Ni ,  Stephen A. St. Onge ,  Jiansheng Xu

发明人： Robert A. Groves ,  Wan Ni ,  Stephen A. St. Onge ,  Jiansheng Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F2217/82

摘要： Systems and methods are provided for capturing mutual coupling effects between an integrated circuit chip and chip package using electronic design automation (EDA) tools. Specifically, a method is provided that is implemented in a computer infrastructure for designing an integrated circuit chip. The method includes compiling process technology parameters that describe electrical behavior for a chip-package coupling and a package of the integrated circuit chip. The method also includes generating a parasitic technology file to include the compiled process technology parameters.

摘要翻译： 提供了使用电子设计自动化（EDA）工具捕获集成电路芯片和芯片封装之间的互耦效应的系统和方法。 具体地说，提供了一种在用于设计集成电路芯片的计算机基础设施中实现的方法。 该方法包括编译描述芯片封装耦合和集成电路芯片封装的电气行为的工艺技术参数。 该方法还包括生成寄生技术文件以包括编译过程技术参数。