公开(公告)号：US06891359B2

公开(公告)日：2005-05-10

申请号：US10248506

申请日：2003-01-24

申请人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

发明人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

IPC分类号： G01N27/00 ,  G01R27/00 ,  G01R31/02 ,  G01R31/28

CPC分类号： G01R31/2855

摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.

摘要翻译： 一种用于预测门可靠性的方法和系统。 该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。 优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。 更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分故障，确定第一个失败和第二个失败之间的关系，并且n ^{th 失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。 如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。 这种关系可以量化。}

公开(公告)号：US07298161B2

公开(公告)日：2007-11-20

申请号：US11088953

申请日：2005-03-24

申请人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

发明人： Kerry Bernstein ,  Ronald J. Bolam ,  Edward J. Nowak ,  Alvin W. Strong ,  Jody J. Van Horn ,  Ernest Y. Wu

IPC分类号： G01R31/26

CPC分类号： G01R31/2855

摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.

摘要翻译： 一种用于预测门可靠性的方法和系统。 该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。 优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。 更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。 如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。 这种关系可以量化。

公开(公告)号：US06437594B1

公开(公告)日：2002-08-20

申请号：US09528350

申请日：2000-03-17

申请人： Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

发明人： Ronald J. Bolam ,  Andres Bryant ,  Edward J. Nowak ,  Minh H. Tong

IPC分类号： G01R2722

CPC分类号： G01R31/3004

摘要： A monitor for detecting pass gate leakage in a silicon on insulator device and a method for using the same is described herein. A pulse generator supplies a signal to a set of buffers connected in parallel, which pass on a signal to the source side of a series of NFETs. The plurality of NFETs are ordered by increasing channel widths. The NFETs have grounded gates, and therefore will not pass current due to field effects. Each NFET is connected to a latch, and the latches are originally set to the same state. When the signal supplied to the NFET drops from high to low, pass gate leakage will occur through the channel of each NFET. If pass gate leakage through any given NFET is sufficient, the latch will change states. The latch output signal is sent to a shift register, which can be made to output information. By incorporating the monitor on the chip, pass gate leakage tolerances and specifications can be established in-line during manufacture.

摘要翻译： 这里描述了一种用于检测绝缘体上硅器件中的漏极泄漏的监视器及其使用方法。 脉冲发生器将信号提供给并联连接的一组缓冲器，该缓冲器将信号传递到一系列NFET的源极侧。 通过增加通道宽度来排列多个NFET。 NFET具有接地栅极，因此由于场效应而不会通过电流。 每个NFET连接到一个锁存器，并且锁存器最初设置为相同的状态。 当提供给NFET的信号从高到低时，通过每个NFET的通道将发生栅极泄漏。 如果通过任何给定NFET的漏极泄漏就足够了，锁存器将改变状态。 锁存器输出信号发送到移位寄存器，可以输出信息。 通过将显示器结合在芯片上，可以在制造过程中在线建立传递门泄漏公差和规格。

公开(公告)号：US07777276B2

公开(公告)日：2010-08-17

申请号：US11969339

申请日：2008-01-04

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US20100203689A1

公开(公告)日：2010-08-12

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US07368355B2

公开(公告)日：2008-05-06

申请号：US11458250

申请日：2006-07-18

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US07115920B2

公开(公告)日：2006-10-03

申请号：US10709076

申请日：2004-04-12

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L27/10

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。

公开(公告)号：US06580293B1

公开(公告)日：2003-06-17

申请号：US09683325

申请日：2001-12-14

申请人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

发明人： Kerry Bernstein ,  Peter E. Cottrell ,  Stephen V. Kosonocky ,  David Meltzer ,  Edward J. Nowak ,  Kevin J. Nowka ,  Norman J. Rohrer

IPC分类号： H03K19096

CPC分类号： H03K19/1737 ,  H03K3/356113 ,  H03K19/0963

摘要： A differential logic circuit (20, 120, 220, 320, 420 and 520) designed to ensure stability of the output of the circuit. The logic circuit includes a differential load structure (22, 122, 222, 322, 422) that is connected to evaluate transistors (50, 52, 54, 56). In several embodiments, the outputs of the load transistors (30, 32) in the differential load structure are connected to the bodies of the evaluate transistors. In the other embodiments, the outputs of the load transistors in the differential structure are connected to one of the gates of a double-gated evaluate transistors. Level-shifting output buffers (160, 178) are used in connection with the embodiments of the invention that do not include double-gated evaluate transistors.

摘要翻译： 设计用于确保电路输出的稳定性的差分逻辑电路（20,120,220,320,420和520）。 逻辑电路包括被连接以评估晶体管（50,52,54,56）的差分负载结构（22,122,222,322,422）。 在几个实施例中，差分负载结构中的负载晶体管（30,32）的输出连接到评估晶体管的主体。 在其他实施例中，差分结构中的负载晶体管的输出连接到双门控评估晶体管的栅极之一。 结合本发明的不包括双门控评估晶体管的实施例，使用电平移位输出缓冲器（160,178）。

公开(公告)号：US06433372B1

公开(公告)日：2002-08-13

申请号：US09527863

申请日：2000-03-17

申请人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

发明人： Eric Adler ,  Kerry Bernstein ,  John J. Ellis-Monaghan ,  Jenifer E. Lary ,  Edward J. Nowak ,  Norman J. Rohrer

IPC分类号： H01L2972

CPC分类号： H01L29/66484

摘要： A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

摘要翻译： 具有减小的扩散电容，自补偿有效沟道长度，改进的短沟道效应控制和增强的密度的多重FET。 通过在衬底上设置多个分离的绝缘栅来形成FET，包括在每个栅极的至少四个表面上形成绝缘材料，在绝缘栅之间的衬底上形成介电层，沉积和平坦化导电材料层 绝缘栅极之间和之间以及绝缘栅极顶表面之间的绝缘材料，以及将多个绝缘栅极中的两个远端绝缘栅极的一部分附近并在下方的基底上注入扩散区域。

公开(公告)号：US07964466B2

公开(公告)日：2011-06-21

申请号：US12762427

申请日：2010-04-19

申请人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

发明人： Kerry Bernstein ,  Edward J. Nowak ,  BethAnn Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/045 ,  H01L29/66795

摘要： A drive strength tunable FinFET, a method of drive strength tuning a FinFET, a drive strength ratio tuned FinFET circuit and a method of drive strength tuning a FinFET, wherein the FinFET has either at least one perpendicular and at least one angled fin or has at least one double-gated fin and one split-gated fin.

摘要翻译： 驱动强度可调谐FinFET，FinFET的驱动强度调谐方法，驱动强度比调谐FinFET电路和FinFET的驱动强度调谐方法，其中FinFET具有至少一个垂直和至少一个成角度的鳍或具有 最少一个双门翅和一个分闸门。