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公开(公告)号：US5557638A
公开(公告)日：1996-09-17
申请号：US212669
申请日：1994-03-10
申请人： Kevin D. Fisher , Ho W. Wong-Lam , Johannes W. M. Bergmans , Frits A. Steenhof , Johannes O. Voorman
发明人： Kevin D. Fisher , Ho W. Wong-Lam , Johannes W. M. Bergmans , Frits A. Steenhof , Johannes O. Voorman
IPC分类号： H04L25/03 , H03K5/08 , H03M13/23 , H04L25/06 , H04L25/12 , H04L25/30 , H04L25/34 , H04L25/49
CPC分类号： H03K5/088 , H04L25/061 , H04L25/12
摘要： In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.
摘要翻译： 在包括经由信道（4）耦合到接收机（6）的发射机（2）的数字传输系统中，将检测信号rk与多个参考值进行比较，以确定目的地符号+ E，cir a + EE k。 由于接收信号rk的大小预先不知道，所以检测信号与参考值之间的比率将由适配电路（16）根据接收到的信号和作出的决定来确定。 然后可能出现这样的问题，即由于检测信号和参考值之间的比率的最初错误的值不是正确的适应。 通过识别这种情况，因为缺少符号+ E，cir a + EE k的特定值，在这种情况下，可以通过校正电路（18）使所述比值达到这样的值，即所有的+ E， 再次出现cir a + EE k。
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公开(公告)号：US5461644A
公开(公告)日：1995-10-24
申请号：US86814
申请日：1993-07-02
CPC分类号： H03M13/6502 , H03M13/41
摘要： Viterbi detector for a channel having a memory length 1, where no more than two survivors with an associated difference metric are updated. In the prior-art Viterbi detector of this type the new difference metric is from the previous difference metric by use of a saturation function. If the channel parameters differ from the values assumed for the calculation of the difference metric, the performance of the prior-art detector will rapidly degrade. In the detector according to the invention the new difference metric is derived from a combination of the saturation function of the previous difference metric and a correction signal which is a measure for the channel parameter difference.
摘要翻译： 用于具有存储器长度1的通道的维特比检测器，其中不超过具有相关差异度量的两个幸存者被更新。 在这种类型的现有维特比检测器中，新的差异度量是通过使用饱和函数从先前的差值度量。 如果信道参数与计算差值度量的值不同，则现有技术检测器的性能将迅速降低。 在根据本发明的检测器中，新的差异度量是从先前差值度量的饱和函数和作为信道参数差的度量的校正信号的组合导出的。
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公开(公告)号：US5487085A
公开(公告)日：1996-01-23
申请号：US262726
申请日：1994-06-20
CPC分类号： H04L25/03038 , H04L2025/03477 , H04L2025/03617
摘要： In a digital transmission system comprising a transmitter (2) connected to a receiver (6) through a channel (4), this receiver comprises an equalizer (8) which includes an equalization filter (12) with output signals from which a sum weighted with weight factors is determined. The output signal of the equalizer is applied to a detector. According to the inventive idea a correction signal for correcting the coefficients w of the equalizer is derived from w.sub.k =w.sub.k-1 +Ma.sub.k e.sub.k, where a.sub.k is the vector of a plurality of successive detected symbols, and e.sub.k is a difference between the current input signal of the detector and a reconstructed ideal input signal of the detector.
摘要翻译： 在包括通过信道（4）连接到接收机（6）的发射机（2）的数字传输系统中，该接收机包括均衡器（8），该均衡器（8）包括均衡滤波器（12），输出信号与 确定体重因子。 均衡器的输出信号被施加到检测器。 根据本发明，用于校正均衡器的系数w的校正信号从wk = wk-1 +Mâkek导出，其中â是多个连续检测符号的向量，ek是当前输入信号之间的差 的检测器和重建的检测器的理想输入信号。
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公开(公告)号：US20120275591A1
公开(公告)日：2012-11-01
申请号：US13458865
申请日：2012-04-27
IPC分类号： H04M1/76
CPC分类号： H04M11/062 , H04B3/32
摘要： Methods, apparatuses (e.g., DSL system hardware, DSL systems, vectoring control entities), techniques, systems, etc. are used for initializing one or more DSL lines joining a vectored DSL line group operating in Showtime. A super-periodic orthogonal pilot sequence from a set of super-periodic orthogonal pilot sequences is assigned to each joining DSL line, wherein each such super-periodic orthogonal pilot sequence in the set has length L and is orthogonal to other sequences in the set over length T. These super-periodic orthogonal pilot sequences are used on the joining DSL lines to generate at least T sync-symbols worth of initialization data, which is processed to generate initialization data and FEXT mitigation coefficients for use when the joining DSL lines become part of the vectored DSL line group.
摘要翻译： 方法，装置（例如，DSL系统硬件，DSL系统，向量控制实体），技术，系统等用于初始化连接在Showtime中操作的向量DSL线路组的一个或多个DSL线路。 从一组超周期正交导频序列的超周期正交导频序列被分配给每个加入DSL线，其中集合中的每个这样的超周期正交导频序列具有长度L，并且与组中的其他序列正交 这些超周期正交导频序列用于加入DSL线路以产生至少T个同步符号的初始化数据，其被处理以产生初始化数据和当加入DSL线路成为部分时使用的FEXT缓解系数 的矢量DSL线组。
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公开(公告)号：US20110080938A1
公开(公告)日：2011-04-07
申请号：US12997222
申请日：2009-06-09
申请人： Kevin D. Fisher , Nicholas P. Sands
发明人： Kevin D. Fisher , Nicholas P. Sands
IPC分类号： H04B1/38
CPC分类号： H04B3/32 , H04M3/2209 , H04M3/304 , H04M3/34 , H04M11/062
摘要： A vector DSL system includes a plurality of modems, which may be multi-port devices. Unprocessed user data is extracted from the modems and passed through a private vectoring data routing apparatus to one or more vectoring modules, such as vectoring cards. Each vectoring module includes one or more vector processors that include processing units configured to process the unprocessed user data on the basis of all modems' data for a given DSL tone grouping. Processing of the unprocessed user data removes the effects of FEXT from upstream and downstream user data and returns the processed user data to the modems using the vectoring data routing apparatus, which can be a specialized data transmission network utilizing one or more vector routers.
摘要翻译： 矢量DSL系统包括多个调制解调器，其可以是多端口设备。 从调制解调器提取未处理的用户数据，并通过专用向量化数据路由装置传送到一个或多个向量模块，例如向量卡。 每个矢量模块包括一个或多个矢量处理器，其包括被配置为基于给定DSL音调分组的所有调制解调器的数据来处理未处理的用户数据的处理单元。 未处理的用户数据的处理从上游和下游用户数据中消除FEXT的影响，并使用向量化数据路由装置将处理过的用户数据返回到调制解调器，矢量化数据路由装置可以是利用一个或多个向量路由器的专用数据传输网络。
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公开(公告)号：US5825318A
公开(公告)日：1998-10-20
申请号：US769823
申请日：1996-12-19
申请人： Ara Patapoutian , Kevin D. Fisher , Bruce D. Buch
发明人： Ara Patapoutian , Kevin D. Fisher , Bruce D. Buch
CPC分类号： G11B5/59605 , G11B20/10009 , G11B21/085 , G11B21/106 , G11B5/5547 , G11B5/59655 , H03M1/201 , G11B20/1258
摘要： An analog-to-digital converter circuit in a sampling data detection channel of a disk drive synchronously samples user data in the data track areas at a first quantization resolution and samples servo bursts from the spoke areas at a second quantization resolution effectively greater than said first quantization resolution. An offset circuit provides a predetermined analog offset signal to a combining circuit which combines it with an incoming analog signal to provide a composite signal during a spoke servo burst sampling interval. An analog-to-digital converter samples the composite signal during the servo spoke burst sampling interval, and synchronously samples the analog signal during a user data sampling interval. A digital averaging circuit averages the servo spoke samples over a predetermined averaging interval to provide averaged burst samples having increased bit resolution.
摘要翻译： 磁盘驱动器的采样数据检测通道中的模拟 - 数字转换器电路以第一量化分辨率同步采样数据轨道区域中的用户数据，并且以比第二量化分辨率有效地大的第二量化分辨率从轮辐区域采样伺服脉冲串 量化分辨率。 偏移电路向组合电路提供预定的模拟偏移信号，该组合电路将其与输入模拟信号组合，以在辐射伺服脉冲串采样间隔期间提供复合信号。 模数转换器在伺服轮询突发采样间隔期间对复合信号进行采样，并在用户数据采样间隔期间同步采样模拟信号。 数字平均电路在预定的平均间隔上对伺服轮辐样本进行平均，以提供具有增加的比特分辨率的平均突发样本。
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公开(公告)号：US08687497B2
公开(公告)日：2014-04-01
申请号：US13002213
申请日：2009-06-30
申请人： Nicholas P. Sands , Kevin D. Fisher
发明人： Nicholas P. Sands , Kevin D. Fisher
IPC分类号： G01R31/08
摘要： A reduced-memory vectored DSL system includes methods and apparatus for reducing the bandwidth and memory storage demands on a vectored DSL system in which FEXT data is transmitted and stored. An upstream-end device such as a DSLAM communicates with a plurality of downstream-end devices such as CPE modems. When test signal data, such as training and/or tracking data, is sent to determine FEXT characteristics of the DSL system, error signals are available for all or substantially all of the upstream and/or downstream frequency band DSL tones used in the system. Dividing a frequency band into sub-bands, only a subset of tones in each sub-band is used for deriving FEXT data, such as a FEXT channel response, FEXT channel coefficients and/or FEXT cancellation coefficients. For tones in the sub-band subsets, full-precision FEXT data values can be derived. For other tones, approximations of the FEXT data can be derived.
摘要翻译： 减少存储器向量的DSL系统包括用于减少其中发送和存储FEXT数据的向量DSL系统的带宽和存储器存储需求的方法和装置。 诸如DSLAM的上游设备与多个下游端设备（例如CPE调制解调器）通信。 当测试信号数据（例如训练和/或跟踪数据）被发送以确定DSL系统的FEXT特性时，错误信号可用于系统中使用的所有或基本上所有上游和/或下游频带DSL音调。 将频带划分为子带，每个子带中仅有一个音调子集用于导出FEXT数据，例如FEXT信道响应，FEXT信道系数和/或FEXT抵消系数。 对于子带子集中的音调，可以导出全精度FEXT数据值。 对于其他色调，可以导出FEXT数据的近似值。
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8.发明授权Bit-interleaved rate 16/17 modulation code with three-way byte-interleaved ECC 失效具有三位字节交错ECC的位交错速率16/17调制码
公开(公告)号：US5757822A
公开(公告)日：1998-05-26
申请号：US518945
申请日：1995-08-24
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , G11B20/18 , H03M7/14 , H03M13/27 , H03M13/00 , H03M5/00 , H03M7/00
CPC分类号： G11B20/1866 , G11B20/10009 , G11B20/1426 , H03M13/27 , G11B2020/1434 , G11B2020/1446
摘要： A modulation method generates a rate 16/17 (d=0, G=7/I=11) modulation code for transferring user digital data bytes having a three-way ECC interleave through a data transfer channel in accordance with the steps of: shuffling the user data bytes in order to rearrange an order of the bytes in a predetermined manner and putting out A.sub.i B.sub.i byte pairs, encoding eight bits of the Ai bytes of the AiBi byte pairs in accordance with a predetermined rate 8/9 modulation code to produce nine code bits a0-a8, and interleaving the nine code bits a0-a8 of each Ai byte with eight unencoded bits of each Bi byte in accordance with a predetermined bitwise interleave pattern to generate the rate 16/17 modulation code. A preferred code and circuitry for the modulation method are also described.
摘要翻译： 调制方法根据以下步骤生成用于通过数据传送通道传送具有三路ECC交错的用户数字数据字节的速率16/17（d = 0，G = 7 / I = 11）调制码：洗牌 用户数据字节，以便以预定方式重新排列字节顺序并输出AiBi字节对，根据预定速率8/9调制码对AiBi字节对的Ai字节的8位进行编码，以产生9 代码比特a0-a8，并且根据预定的按位交织模式，将每个Ai字节的九个码比特a0-a8与每个Bi字节的八个未编码比特交织，以生成速率16/17调制码。 还描述了调制方法的优选代码和电路。
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公开(公告)号：US5606466A
公开(公告)日：1997-02-25
申请号：US546628
申请日：1995-10-23
申请人： Kevin D. Fisher , Bruce Buch , Thomas Lau , Pablo A. Ziperovich
发明人： Kevin D. Fisher , Bruce Buch , Thomas Lau , Pablo A. Ziperovich
CPC分类号： G11B20/10009 , G11B20/1258 , G11B20/1426
摘要： A new method for overlapping block read events in a disk drive having synchronously sampled data detection channels is presented. In particular, the new method is for overlapping read back processing by real-time and digital signal processing of first and second data blocks from a storage medium. The method includes steps of clocking real-time and digital signal processes by a clock synchronized to the first data block while the first data block is passing by a data transducer head, clocking the digital signal processes for the first data block by an asynchronous clock operating at a nominal data clocking rate after the first data block has passed by the data transducer head and before a clock has synchronized to the second data block following the first data block, and clocking real-time signal processes for the second data block and completing clocking of the digital processes for the first data block by a clock synchronized to the second data block passing by the data transducer head. The storage medium can be a magnetic hard disk, magnetic tape, or an optical disk, for example.
摘要翻译： 提出了一种用于在具有同步采样数据检测通道的磁盘驱动器中重叠块读取事件的新方法。 特别地，新方法是通过来自存储介质的第一和第二数据块的实时和数字信号处理来重叠读回处理。 该方法包括以下步骤：通过与第一数据块同步的时钟对实时和数字信号处理进行计时，同时第一数据块通过数据传感器头，通过异步时钟操作为第一数据块的数字信号处理计时 在第一数据块经过数据变换器头之后并且在时钟已经与第一数据块之后的第二数据块同步之后的标称数据时钟速率，以及对第二数据块的实时信号处理进行计时并完成时钟 通过与数据传感器头通过的第二数据块同步的时钟来产生第一数据块的数字处理。 存储介质可以是例如磁性硬盘，磁带或光盘。
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10.发明授权Adaptive decision feedback equalizer apparatus for processing information stored on digital storage media 失效用于处理存储在数字存储介质上的信息的自适应判决反馈均衡器装置
公开(公告)号：US5132988A
公开(公告)日：1992-07-21
申请号：US622106
申请日：1990-12-03
CPC分类号： G11B20/10046 , G11B20/10009 , H04L25/03057
摘要： Adaptive decision feedback equalizer apparatus for processing information stored on disk or tape media or the like including a data input buffer (34), a gain acquisition circuit (42), a timing acquisition circuit (40) operative to generate timing error signals for controlling the sampling phase of the read signals input to the input buffer, a synchronizing circuit (44) for generating sync detect signals and polarity signals, an FIR filter (36) for generating linear filter output signals, register means (39), feedforward update logic (38) for adjusting the equalizer coefficient signals to develop undated coefficient signals, a dual ported RAM (50) for storing a plurality of the equalizer coefficient signals, feedback logic (48) responsive to the linear filter output signals, equalizer coefficient signals obtained from the RAM, and train data signals, and operative to compute the equalizer error signals and equalizer output signals, feedback update logic (52) for adjusting the values of the coefficient signals for input back to the RAM as update signals, steady-state timing logic (54), and a controller (46) responsive to the polarity signals and the sync detect signals and operative to generate the train data signals and mode control signals for causing the equalizer apparatus to operate in either a set-up/test mode or a run mode, whereby read signals input from a storage media are sampled, amplified and digitally processed to decode stored information bits with the result that, as compared to prior art systems, storage density may be increased and error rate decreased.
摘要翻译： 用于处理存储在磁盘或磁带介质等上的信息的自适应判决反馈均衡器装置，包括数据输入缓冲器（34），增益获取电路（42），定时获取电路（40），用于产生定时误差信号， 输入到输入缓冲器的读取信号的采样相位，用于产生同步检测信号和极性信号的同步电路（44），用于产生线性滤波器输出信号的FIR滤波器（36），寄存器装置（39），前馈更新逻辑 38），用于调整均衡器系数信号以产生未标注的系数信号;双端口RAM（50），用于存储多个均衡器系数信号，响应于线性滤波器输出信号的反馈逻辑（48），从 RAM和训练数据信号，并且可操作以计算均衡器误差信号和均衡器输出信号，反馈更新逻辑（52）用于调整 用于作为更新信号输入到RAM的系数信号，稳态定时逻辑（54）和响应于极性信号和同步检测信号的控制器（46），并用于产生列车数据信号和模式控制信号 用于使均衡器装置在设置/测试模式或运行模式下操作，由此从存储介质输入的读取信号被采样，放大和数字处理以解码存储的信息位，结果是与之前的 艺术系统，存储密度可能会增加，错误率降低。
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