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1.发明授权Apparatus and method for recording a digital information signal in slant tracks on a record carrier 失效用于在记录载体上的倾斜轨道中记录数字信息信号的装置和方法公开(公告)号：US06418270B1
公开(公告)日：2002-07-09
申请号：US09451278
申请日：1999-11-30
IPC分类号： H04N591
CPC分类号： G11B20/10 , G11B20/1809 , G11B27/005 , G11B27/3027 , G11B2220/90
摘要： A signal processing technique for generating and processing trick play information for recording on a record carrier is used in an apparatus for recording a digital information signal onto a record carrier, in which the apparatus includes a first error correction encoder for error correcting trick play sync blocks generated from the digital information signal, a second error correction encoder for error correcting sync blocks formed from sync blocks of the digital information signal and the error corrected trick play sync blocks, and a third error correction encoder for error correcting each of the error corrected sync blocks. In the technique, the order that the trick play sync blocks provided by the first error correction encoder to the second error correction encoder is not the same as the order in which the third error correction encoder supplies the trick play sync blocks to the writing heads.
摘要翻译： 在用于在记录载体上记录数字信息信号的装置中使用用于产生和处理用于在记录载体上记录的特技播放信息的信号处理技术，其中该装置包括用于纠错特技播放同步块的第一纠错编码器 从数字信息信号产生的第二纠错编码器，用于对由数字信息信号和纠错特技播放同步块的同步块形成的同步块进行纠错的第二纠错编码器;以及第三纠错编码器，用于纠错每个纠错的同步 块。 在该技术中，由第一纠错编码器向第二纠错编码器提供的特技播放同步块的顺序与第三纠错编码器向写入头提供特技播放同步块的顺序不同。
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公开(公告)号：US4947380A
公开(公告)日：1990-08-07
申请号：US208186
申请日：1988-06-16
申请人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
发明人： Adrianus T. Van Zanten , Hendrikus J. M. Veendrick , Frits A. Steenhof , Peter H. Frencken , Antonius H. H. J. Nillesen , Cornelis G. L. M. Van Der Sanden
CPC分类号： G11C19/287 , G11C27/04
摘要： The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out (as background video memory); 2.times.2 parallel-in, demultiplex/multiplex mode, for example for 100 Hz TV; scan mode; parallel-in-recirculation mode; "shortened" memory, for example for 525-line system, etcetera. Control is realized via a decoding and timing block in which a multi-bit control word is serially input and decoded. In a scan mode (for example, as a teletext memory), the memory sections are scanned one-by-one under the control of a separate scan register in which a scan bit (logic 1) is step-wise shifted until all sections have been read. Via a data output, the scan bit is transferred, for example to the scan register of a further memory device (via its serial data input) which is connected in series with the former memory device.
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3.发明授权Data processing system in which unreliable words in the memory are replaced by an unreliability indicator 失效数据处理系统，其中存储器中的不可靠字被替换为不可靠性指示符
公开(公告)号：US4641310A
公开(公告)日：1987-02-03
申请号：US666710
申请日：1984-10-31
CPC分类号： G11B20/18 , G06F11/10 , G11B20/1813
摘要： A data processing system comprising a memory receives data in the form of data blocks. Such a data block contains at least one data word and check bits. On the basis of the check bits it is vertified whether the data block contains reliable or unreliable data words. The unreliable data words are not written into the memory but are replaced by an unreliability indicator which is written into the memory at the address reserved for the unreliable dataword in question.
摘要翻译： 包括存储器的数据处理系统以数据块的形式接收数据。 这样的数据块包含至少一个数据字和校验位。 在校验位的基础上，数据块是否包含可靠或不可靠的数据字是无偏的。 不可靠的数据字不被写入存储器中，而是被不可靠性指示符代替，该不可靠性指示符被写入存储器中，用于为所讨论的不可靠数据字保留。
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公开(公告)号：US5557638A
公开(公告)日：1996-09-17
申请号：US212669
申请日：1994-03-10
申请人： Kevin D. Fisher , Ho W. Wong-Lam , Johannes W. M. Bergmans , Frits A. Steenhof , Johannes O. Voorman
发明人： Kevin D. Fisher , Ho W. Wong-Lam , Johannes W. M. Bergmans , Frits A. Steenhof , Johannes O. Voorman
IPC分类号： H04L25/03 , H03K5/08 , H03M13/23 , H04L25/06 , H04L25/12 , H04L25/30 , H04L25/34 , H04L25/49
CPC分类号： H03K5/088 , H04L25/061 , H04L25/12
摘要： In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.
摘要翻译： 在包括经由信道（4）耦合到接收机（6）的发射机（2）的数字传输系统中，将检测信号rk与多个参考值进行比较，以确定目的地符号+ E，cir a + EE k。 由于接收信号rk的大小预先不知道，所以检测信号与参考值之间的比率将由适配电路（16）根据接收到的信号和作出的决定来确定。 然后可能出现这样的问题，即由于检测信号和参考值之间的比率的最初错误的值不是正确的适应。 通过识别这种情况，因为缺少符号+ E，cir a + EE k的特定值，在这种情况下，可以通过校正电路（18）使所述比值达到这样的值，即所有的+ E， 再次出现cir a + EE k。
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公开(公告)号：US4684986A
公开(公告)日：1987-08-04
申请号：US730392
申请日：1985-05-03
摘要： In a television signal memory write circuit which is synchronized by horizontal and vertical synchronizing signal patterns obtained from the television signal to be entered, the mutual positions of these patterns being measured with the aid of a measuring circuit; and depending on this measurement, the vertical synchronizing signal pattern is delayed by a variable delay circuit such that in practice the patterns are prevented from coinciding, thereby preventing a change in the position of a predetermined line number in the television signal memory circuit. This renders the circuit less sensitive to interference.
摘要翻译： 在通过从要输入的电视信号获得的水平和垂直同步信号模式同步的电视信号存储器写入电路中，借助于测量电路来测量这些图案的相互位置; 并且根据该测量，垂直同步信号模式被可变延迟电路延迟，使得在实际中防止图案重合，从而防止电视信号存储电路中预定行号的位置改变。 这使得电路对干扰不太敏感。
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公开(公告)号：US6088828A
公开(公告)日：2000-07-11
申请号：US927886
申请日：1997-09-11
IPC分类号： H03M13/00 , H03M13/09 , H03M13/23 , H03M13/29 , H03M13/37 , H03M13/39 , H03M13/41 , H03M13/45 , H04L1/00 , H04L7/00 , H03M13/33
CPC分类号： H03M13/2933 , H03M13/3738 , H03M13/41 , H03M13/6362 , H03M13/6508 , H03M13/6516 , H04L1/0054 , H04L1/0057 , H04L1/0063 , H04L1/0065 , H04L1/0068 , H03M13/09 , H03M13/3776 , H04L2001/0093
摘要： In order to find the position of the boundary between transmitted codewords, in a receiver a reliability measure for two possible positions are compared. If a relative difference measure of these reliability measure exceeds a predetermined threshold value, the reliability measure indicating the largest reliability corresponds to the correct position of the boundary between the codewords.
摘要翻译： 为了找到发送码字之间的边界的位置，在接收机中比较两个可能位置的可靠性度量。 如果这些可靠性度量的相对差异度量超过预定阈值，则表示最大可靠性的可靠性度量对应于码字之间的边界的正确位置。
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公开(公告)号：US5018172A
公开(公告)日：1991-05-21
申请号：US489406
申请日：1990-03-05
申请人： Frits A. Steenhof
发明人： Frits A. Steenhof
CPC分类号： G11C19/287
摘要： In a charge-coupled SPS memory device, in which the transport takes place according to the "pushing" principle, it may occur that during the SP transport charge is injected into the substrate and diffuses via the substrate into the memory mat. In order to avoid this undesired injection of charge, the input is provided with means by which it is ensured that the storage site under the input gate is entirely empty during the SP transport.
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8.发明授权SPS type charge coupled device memory suitable for processing video information with increased speed 失效SPS型电荷耦合器件存储器适用于以更快的速度处理视频信息
公开(公告)号：US4992982A
公开(公告)日：1991-02-12
申请号：US252847
申请日：1988-10-03
申请人： Frits A. Steenhof
发明人： Frits A. Steenhof
CPC分类号： G11C27/04 , G11C19/287
摘要： An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different procedures for generating the de-interlacing clocks for the odd channels and for the even channels of the parallel section. These procedures are carried out sequentially with an adjustable difference in time.
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9.发明授权Charge-coupled device with varible storage capacity and constant clock frequency 失效具有可变存储容量和恒定时钟频率的电荷耦合器件
公开(公告)号：US4868665A
公开(公告)日：1989-09-19
申请号：US183869
申请日：1988-04-19
IPC分类号： G11C27/04 , H01L21/339 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/762 , H04N5/335 , H04N5/907
摘要： In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n-phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed. By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.
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公开(公告)号：US4851908A
公开(公告)日：1989-07-25
申请号：US178741
申请日：1988-04-07
CPC分类号： H04N7/0132 , H04N7/0105 , Y10S348/91
摘要： A field number doubling circuit has a measuring circuit (25) for determining the starting instant of a second read operation of a memory circuit (3) with respect to that of a first read operation in such a way that a display of a field number doubled television signal, even for a non-standard television signal to be doubled in field number, does not exhibit any flicker at the field frequency of the last-mentioned signal. Furthermore, the measuring circuit can determine the most favorable waiting period (B) between a write operation and a first read operation, the waiting period (A) between a vertical synchronizing pulse (V) and the start of a memory write operation, and a value for the waiting period (C) between the start of a memory read operation and the start of vertical deflection of a picture display section (13). A counter circuit (29) which can be controlled by means of the measuring circuit is provided for the controllable periods.
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