公开(公告)号：US07173852B2

公开(公告)日：2007-02-06

申请号：US11253531

申请日：2005-10-18

申请人： Sergey Anatolievich Gorobets ,  Reuven Elhamias ,  Carlos J. Gonzalez ,  Kevin M. Conley

发明人： Sergey Anatolievich Gorobets ,  Reuven Elhamias ,  Carlos J. Gonzalez ,  Kevin M. Conley

IPC分类号： G11C11/34

CPC分类号： G06F11/106 ,  G06F11/1068 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/76

摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase. Data is rewritten when severe errors are found during read operations. Portions of data are corrected and copied within the time limit for read operation. Corrected portions are written to dedicated blocks.

摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。 在读取操作期间发现严重错误时，数据被重写。 部分数据在读取操作的时限内得到纠正和复制。 校正的部分被写入专用块。

公开(公告)号：US07408834B2

公开(公告)日：2008-08-05

申请号：US11671394

申请日：2007-02-05

申请人： Kevin M. Conley ,  Reuven Elhamias

发明人： Kevin M. Conley ,  Reuven Elhamias

IPC分类号： G11C8/00

CPC分类号： G06F12/0862 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/2146 ,  G06F2212/282 ,  G06F2212/502

摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

摘要翻译： 介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。 缓存策略包括直写，回写和预读。 直写和回写策略可能会提高速度。 预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。 会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。

公开(公告)号：US07173863B2

公开(公告)日：2007-02-06

申请号：US10796575

申请日：2004-03-08

申请人： Kevin M. Conley ,  Reuven Elhamias

发明人： Kevin M. Conley ,  Reuven Elhamias

IPC分类号： G11C7/00

CPC分类号： G06F12/0862 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/2146 ,  G06F2212/282 ,  G06F2212/502

摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

摘要翻译： 介于非易失性存储器和主机之间的缓冲器高速缓存可被划分成可以不同策略操作的段。 缓存策略包括直写，写入和预读。 直写和回写策略可能会提高速度。 预读高速缓存允许在缓冲器高速缓存和非易失性存储器之间更有效地使用总线。 会话命令允许通过保证防止功率损耗来将数据保存在易失性存储器中。

公开(公告)号：US09678877B2

公开(公告)日：2017-06-13

申请号：US12138708

申请日：2008-06-13

申请人： Kevin M. Conley ,  Reuven Elhamias

发明人： Kevin M. Conley ,  Reuven Elhamias

IPC分类号： G06F12/00 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0804

CPC分类号： G06F12/0862 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/214 ,  G06F2212/2146 ,  G06F2212/282 ,  G06F2212/502

摘要： A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

公开(公告)号：US09245634B2

公开(公告)日：2016-01-26

申请号：US12621011

申请日：2009-11-18

申请人： Kevin M. Conley

发明人： Kevin M. Conley

IPC分类号： G11C16/20 ,  G06F9/44 ,  G06F9/445

CPC分类号： G11C16/20 ,  G06F9/445

摘要： A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.

公开(公告)号：US08504798B2

公开(公告)日：2013-08-06

申请号：US10749831

申请日：2003-12-30

申请人： Kevin M. Conley ,  Carlos J. Gonzalez

发明人： Kevin M. Conley ,  Carlos J. Gonzalez

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F2212/7202

摘要： A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made.

摘要翻译： 一种类型的非易失性存储器系统，其具有一起擦除的存储器单元的块，并且可以以每块的大量页面为单位从擦除状态编程。 如果要更新块的几页数据，则更新的页面被写入为此目的提供的另一个块。 然后，有效的原始和更新的数据在稍后的时间被组合，当这样做不影响存储器的性能时。 然而，如果要更新块的大量页面的数据，则更新的页面被写入未使用的擦除块，并且未改变的页面也被写入到相同的未使用的块。 通过不同的处理几页的更新，当进行小型更新时，内存性能得到改善。

公开(公告)号：USD648729S1

公开(公告)日：2011-11-15

申请号：US29366680

申请日：2010-07-28

申请人： John Beekley ,  Lev M. Bolotin ,  Gary Bordenkircher ,  James Carlton ,  Kevin M. Conley ,  Robert Hubler ,  Simon B. Johnson ,  Andrew J. Paul

设计人： John Beekley ,  Lev M. Bolotin ,  Gary Bordenkircher ,  James Carlton ,  Kevin M. Conley ,  Robert Hubler ,  Simon B. Johnson ,  Andrew J. Paul

公开(公告)号：US07904788B2

公开(公告)日：2011-03-08

申请号：US11556615

申请日：2006-11-03

申请人： Yigal Brandman ,  Kevin M. Conley

发明人： Yigal Brandman ,  Kevin M. Conley

IPC分类号： H03M13/00

CPC分类号： G11C11/5642 ,  G06F11/1072 ,  G11C16/26 ,  G11C16/349

摘要： Data is read from a nonvolatile memory array using one or more read voltages that are adjusted during memory life. Programming target voltages and read voltages may be adjusted together over memory life to map memory states to an increasingly wide threshold window. Individual memory states are mapped to sub-ranges that are made wider, reducing errors.

摘要翻译： 使用在存储器寿命期间调整的一个或多个读取电压从非易失性存储器阵列读取数据。 编程目标电压和读取电压可以在存储器寿命中一起调整，以将存储器状态映射到越来越宽的阈值窗口。 单个内存状态映射到更广泛的子范围，从而减少错误。

公开(公告)号：US07904783B2

公开(公告)日：2011-03-08

申请号：US11536327

申请日：2006-09-28

申请人： Yigal Brandman ,  Kevin M. Conley

发明人： Yigal Brandman ,  Kevin M. Conley

IPC分类号： G11C29/00 ,  H03M13/29 ,  H03M13/45

CPC分类号： G06F11/1072 ,  G06F11/1068 ,  G11C16/0483 ,  G11C2029/0411

摘要： In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

摘要翻译： 在非易失性存储器系统中，从存储器阵列中读取数据并用于获得似然值，然后提供给软输入软输出解码器。 软输入软输出解码器从输入似然值和根据编码方案先前添加的奇偶校验数据计算输出似然值。

公开(公告)号：US07882299B2

公开(公告)日：2011-02-01

申请号：US11021200

申请日：2004-12-21

申请人： Kevin M. Conley ,  Yoram Cedar

发明人： Kevin M. Conley ,  Yoram Cedar

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0893 ,  G06F12/0246 ,  G06F12/0804 ,  G06F2212/7203 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2207/2245 ,  G11C2216/14

摘要： A method of programming a non-volatile memory array using an on-chip write cache is disclosed. Individual data packets received by the memory system are stored in cache memory. More than one data packet may be stored in this way and then programmed to a single page of the non-volatile array. This results in more efficient use of storage space in the non-volatile array.

摘要翻译： 公开了一种使用片上写高速缓存来编程非易失性存储器阵列的方法。 由存储器系统接收的各个数据分组存储在高速缓冲存储器中。 可以以这种方式存储多于一个数据分组，然后编程到非易失性阵列的单页。 这导致在非易失性阵列中更有效地使用存储空间。