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    Semiconductor fabrication using a collar
    1.
    发明申请
    Semiconductor fabrication using a collar 有权
    使用领的半导体制造

    公开(公告)号：US20050191805A1

    公开(公告)日：2005-09-01

    申请号：US10788977

    申请日：2004-02-27

    Applicant: Kevin Torek ,  Kevin Shea ,  Niraj Rana ,  Zhiping Yin

    Inventor： Kevin Torek ,  Kevin Shea ,  Niraj Rana ,  Zhiping Yin

    IPC: H01L21/20 ,  H01L21/8242 ,  H01L23/31

    CPC classification number: H01L27/10852 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory container. An opening exists between the collar material along a corner of the first memory container and the collar material along a corner of a third memory container.

    Abstract translation: 在一个实施例中，一种方法包括在多个存储器容器之间选择性地沉积套环材料。 沿着存储容器数量的第一存储容器的一侧的套环材料沿着第二存储容器的侧面与套环材料接触。 在沿着第一存储容器的角部的套环材料和沿着第三存储容器的角部的套环材料之间存在开口。

    Semiconductor fabrication using a collar
    3.
    发明授权
    Semiconductor fabrication using a collar 失效
    使用领的半导体制造

    公开(公告)号：US07541635B2

    公开(公告)日：2009-06-02

    申请号：US11490770

    申请日：2006-07-21

    Applicant: Kevin Torek ,  Kevin Shea ,  Niraj B. Rana ,  Zhiping Yin

    Inventor： Kevin Torek ,  Kevin Shea ,  Niraj B. Rana ,  Zhiping Yin

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L27/10852 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a method includes selectively depositing a collar material between a number of memory containers. The collar material along a side of a first memory container of the number of memory containers is in contact with the collar material along a side of a second memory container. An opening exists between the collar material along a corner of the memory container and the collar material along a corner of a third memory container.

    Abstract translation: 在一个实施例中，一种方法包括在多个存储器容器之间选择性地沉积套环材料。 沿着存储容器数量的第一存储容器的一侧的套环材料沿着第二存储容器的侧面与套环材料接触。 在沿着第一存储容器的角部的套环材料和沿着第三存储容器的角部的套环材料之间存在开口。

    Highly selective doped oxide etchant
    5.
    发明授权
    Highly selective doped oxide etchant 有权
    高选择性掺杂氧化物蚀刻剂

    公开(公告)号：US08512587B2

    公开(公告)日：2013-08-20

    申请号：US11830059

    申请日：2007-07-30

    Applicant: Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    Inventor： Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    IPC: B44C1/22 ,  H01L21/302 ,  C03C15/00

    CPC classification number: H01L21/31111 ,  C09K13/08

    Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally, with an inorganic acid, and a pH of 1 or less.

    Abstract translation: 提供了在存在氮化硅，氮化钛和硅材料的情况下选择性地蚀刻掺杂的氧化物材料的蚀刻解决方案，以及利用蚀刻溶液的方法，例如在容器电容器结构的构造中。 蚀刻溶液被配制为氢氟酸和介电常数小于水的有机酸的混合物，任选地与无机酸，pH为1或更小。

    Highly Selective Doped Oxide Etchant
    6.
    发明申请
    Highly Selective Doped Oxide Etchant 有权
    高选择性掺杂氧化物蚀刻剂

    公开(公告)号：US20070262048A1

    公开(公告)日：2007-11-15

    申请号：US11830059

    申请日：2007-07-30

    Applicant: Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    Inventor： Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    IPC: C03C15/00 ,  H01G4/002

    CPC classification number: H01L21/31111 ,  C09K13/08

    Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in the construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally with an inorganic acid, and a pH of 1 or less.

    Abstract translation: 提供了在氮化硅，氮化钛和硅材料的存在下选择性地蚀刻掺杂的氧化物材料的蚀刻解决方案，以及利用蚀刻溶液的方法，例如在容器电容器结构的构造中。 蚀刻溶液配制为氢氟酸和介电常数小于水，任选与无机酸，pH为1或更小的有机酸的混合物。

    Highly selective doped oxide etchant
    7.
    发明申请
    Highly selective doped oxide etchant 审中-公开
    高选择性掺杂氧化物蚀刻剂

    公开(公告)号：US20070207622A1

    公开(公告)日：2007-09-06

    申请号：US11360540

    申请日：2006-02-23

    Applicant: Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    Inventor： Niraj Rana ,  Prashant Raghu ,  Kevin Torek

    IPC: H01L21/302 ,  C03C15/00

    CPC classification number: H01L21/31111 ,  C09K13/08

    Abstract: Etch solutions for selectively etching doped oxide materials in the presence of silicon nitride, titanium nitride, and silicon materials, and methods utilizing the etch solutions, for example, in the construction of container capacitor constructions are provided. The etch solutions are formulated as a mixture of hydrofluoric acid and an organic acid having a dielectric constant less than water, optionally with an inorganic acid, and a pH of 1 or less.

    Abstract translation: 提供了在氮化硅，氮化钛和硅材料的存在下选择性地蚀刻掺杂的氧化物材料的蚀刻解决方案，以及利用蚀刻溶液的方法，例如在容器电容器结构的构造中。 蚀刻溶液配制为氢氟酸和介电常数小于水，任选与无机酸，pH为1或更小的有机酸的混合物。

    Method of forming high aspect ratio structures
    8.
    发明授权
    Method of forming high aspect ratio structures 有权
    形成高纵横比结构的方法

    公开(公告)号：US07932550B2

    公开(公告)日：2011-04-26

    申请号：US11215489

    申请日：2005-08-30

    Applicant: Kevin Torek ,  Kevin Shea ,  Thomas Graettinger

    Inventor： Kevin Torek ,  Kevin Shea ,  Thomas Graettinger

    IPC: H01L27/108

    CPC classification number: H01L28/91 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32134 ,  H01L21/32135 ,  H01L27/10852

    Abstract: An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external surface by an etch process that resists destructive collapse of the conductive structure.

    Abstract translation: 蚀刻工艺包括在基片上提供电介质第一膜和在电介质第一膜上提供牺牲第二膜。 诸如容器电容器的导电结构形成在第一和第二膜的凹部中。 导电结构通过蚀刻工艺暴露于其外表面，该蚀刻工艺抵抗导电结构的破坏性破坏。

    Semiconductor fabrication that includes surface tension control
    9.
    发明申请
    Semiconductor fabrication that includes surface tension control 审中-公开
    包括表面张力控制的半导体制造

    公开(公告)号：US20070173013A1

    公开(公告)日：2007-07-26

    申请号：US11726522

    申请日：2007-03-22

    Applicant: Kevin Torek ,  Kevin Shea

    Inventor： Kevin Torek ,  Kevin Shea

    IPC: H01L21/8244

    CPC classification number: H01L28/40 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31625 ,  H01L27/1085

    Abstract: In one embodiment, a method includes providing a semiconductor substrate that includes a memory container having a double-sided capacitor. The method also includes vapor phase etching a layer adjacent to the side wall of the memory container with a vapor having a surface tension lowering agent.

    Abstract translation: 在一个实施例中，一种方法包括提供包括具有双面电容器的存储容器的半导体衬底。 该方法还包括用具有表面张力降低剂的蒸气相气相蚀刻存储容器侧壁附近的层。

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