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公开(公告)号：US08779485B2
公开(公告)日：2014-07-15
申请号：US13480044
申请日：2012-05-24
IPC分类号： H01L21/02 , H01L23/48 , H01L21/768 , H01L49/02 , H01L27/115
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
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公开(公告)号：US20110062550A1
公开(公告)日：2011-03-17
申请号：US12718691
申请日：2010-03-05
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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公开(公告)号：US08440508B2
公开(公告)日：2013-05-14
申请号：US12718691
申请日：2010-03-05
IPC分类号： H01L21/82 , H01L21/00 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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公开(公告)号：US20120228739A1
公开(公告)日：2012-09-13
申请号：US13480044
申请日：2012-05-24
IPC分类号： H01L29/92
CPC分类号： H01L21/76843 , H01L27/11509 , H01L28/57
摘要： An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.
摘要翻译： 包含FeCap阵列的集成电路。 FeCap阵列在侧面至少部分地被氢阻挡壁包围，并且在顶部被氢阻挡顶板包围。 一种用于至少部分地封闭具有氢阻挡壁和氢阻挡顶板的FeCap阵列的方法。
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公开(公告)号：US07425512B2
公开(公告)日：2008-09-16
申请号：US10721932
申请日：2003-11-25
申请人： Kezhakkedath R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, Jr. , Francis G. Celii
发明人： Kezhakkedath R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, Jr. , Francis G. Celii
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译： 本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。 除了其他步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155， 蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，并且蚀刻剂对氧化铝蚀刻停止层130是选择性的。 氧化铝蚀刻停止层也可用作先进CMOS工艺的后端作为通孔蚀刻停止层。
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6.发明申请Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof 有权具有减少单个位故障的半导体器件及其制造方法公开(公告)号：US20090057736A1
公开(公告)日：2009-03-05
申请号：US11845834
申请日：2007-08-28
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.
摘要翻译： 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。
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7.发明授权Semiconductor device having reduced single bit fails and a method of manufacture thereof 有权具有减少的单位故障的半导体器件及其制造方法公开(公告)号：US07772014B2
公开(公告)日：2010-08-10
申请号：US11845834
申请日：2007-08-28
IPC分类号： H01L29/92
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.
摘要翻译： 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。
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公开(公告)号：US20130062996A1
公开(公告)日：2013-03-14
申请号：US13230350
申请日：2011-09-12
CPC分类号： H01L41/08 , H01L27/20 , H01L41/0533 , H01L41/1134 , H01L41/1136 , H01L41/1138 , H01L41/22 , H01L41/318 , H01L2224/18
摘要： A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.
摘要翻译： 平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。 压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。 在铁电元件上形成至少两个电极。 在压电元件上形成上部氢屏障。 在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。 压电元件与柔性元件重叠。
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9.发明申请Semiconductor Device Having Reduced Single Bit Fails and a Method of Manufacture Thereof 审中-公开具有减少单个位故障的半导体器件及其制造方法公开(公告)号：US20100270601A1
公开(公告)日：2010-10-28
申请号：US12828978
申请日：2010-07-01
IPC分类号： H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/57
摘要： One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.
摘要翻译： 本发明的一个方面提供一种制造具有减少单位故障的FeRAM半导体器件的方法。 该方面包括在位于半导体衬底之上的电介质层内形成电接触，并在电介质层和电接触之上形成第一阻挡层。 第一阻挡层通过沉积多个阻挡层并在其沉积之后致密化每个阻挡层而形成。 这形成了具有相同元素组成的多个阻挡层的堆叠。 该方法还包括在第一阻挡层上形成第二阻挡层，并形成下电容器电极，在下电容器上形成铁电电介质层，以及在铁电介质层上形成上电容器电极。 本文还提供了通过该方法制造的装置。
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公开(公告)号：US08496842B2
公开(公告)日：2013-07-30
申请号：US13230350
申请日：2011-09-12
IPC分类号： B44C1/22
CPC分类号： H01L41/08 , H01L27/20 , H01L41/0533 , H01L41/1134 , H01L41/1136 , H01L41/1138 , H01L41/22 , H01L41/318 , H01L2224/18
摘要： A planar integrated MEMS device has a piezoelectric element on a dielectric isolation layer over a flexible element attached to a proof mass. The piezoelectric element contains a ferroelectric element with a perovskite structure formed over an isolation dielectric. At least two electrodes are formed on the ferroelectric element. An upper hydrogen barrier is formed over the piezoelectric element. Front side singulation trenches are formed at a periphery of the MEMS device extending into the semiconductor substrate. A DRIE process removes material from the bottom side of the substrate to form the flexible element, removes material from the substrate under the front side singulation trenches, and forms the proof mass from substrate material. The piezoelectric element overlaps the flexible element.
摘要翻译： 平面集成MEMS器件在连接到校准块的柔性元件上的介电隔离层上具有压电元件。 压电元件包含在隔离电介质上形成的具有钙钛矿结构的铁电元件。 在铁电元件上形成至少两个电极。 在压电元件上形成上部氢屏障。 在延伸到半导体衬底中的MEMS器件的周边形成有正面侧划分沟槽。 DRIE工艺从衬底的底侧去除材料以形成柔性元件，在正面单面沟槽之下从衬底去除材料，并从衬底材料形成校验物质。 压电元件与柔性元件重叠。
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