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    MAGNETIC DEVICE
    1.
    发明申请
    MAGNETIC DEVICE 有权
    磁性装置

    公开(公告)号：US20130234267A1

    公开(公告)日：2013-09-12

    申请号：US13682737

    申请日：2012-11-21

    Applicant: Ki-joon Kim ,  Hyung-joon Kwon

    Inventor： Ki-joon Kim ,  Hyung-joon Kwon

    IPC: H01L29/82

    CPC classification number: H01L29/82 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

    Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

    Abstract translation: 一种磁体结构，包括：磁性层图案; 以及包括金属玻璃合金并覆盖至少一部分磁体结构的导电图案。

    Galios field processor having dual parallel data path for Bose Chaudhuri Hocquenghem/Reed-Solomon decoder
    3.
    发明授权
    Galios field processor having dual parallel data path for Bose Chaudhuri Hocquenghem/Reed-Solomon decoder 失效
    用于Bose Chaudhuri Hocquenghem / Reed-Solomon解码器的具有双并行数据路径的Galios现场处理器

    公开(公告)号：US06574771B1

    公开(公告)日：2003-06-03

    申请号：US09528676

    申请日：2000-03-20

    Applicant: Hyung-joon Kwon

    Inventor： Hyung-joon Kwon

    IPC: H03M1300

    CPC classification number: H03M13/6561 ,  H03M13/15 ,  H03M13/153 ,  H03M13/1555 ,  H03M13/158

    Abstract: A Galois field processor having a dual parallel data path for a Bose Chaudhuri Hocquenghem/Reed-Solomon (BCH/RS) decoder is provided. The Galois field processor includes a syndrome register block for storing syndrome values transmitted by a syndrome generating block, a correction polynomial register block, a connection polynomial register block, and a discrepancy register block. A dual mode Galois field data path (DMGFDP) includes a first data path for receiving the respective outputs of the syndrome register block, the correction polynomial register block, the connection polynomial register block, and the discrepancy register block, performing predetermined operations related to the even-degree coefficients of correction and connection polynomial, and outputting the even-degree coefficient output. A second data path performs predetermined operations related to the odd-degree coefficients of the correction and connection polynomial and outputs the odd-degree coefficient output. A delta output unit performs predetermined operations related to the even-degree and the odd-degree coefficients of the connections polynomial and outputs the delta output. An output unit outputs the coefficients of an error location polynomial, according to a control signal. Since the Galois processor, in which latency during the operation processes is minimized, has a small area and operates at high speed, the performance of the decoder is greatly improved.

    Abstract translation: 提供了一种具有用于Bose Chaudhuri Hocquenghem / Reed-Solomon（BCH / RS）解码器的双平行数据路径的Galois场处理器。 伽罗瓦域处理器包括用于存储由校正子生成块，校正多项式寄存器块，连接多项式寄存器块和差异寄存器块发送的校正子值的校正子寄存器块。 双模式伽罗瓦域数据路径（DMGFDP）包括用于接收校正子寄存器块，校正多项式寄存器块，连接多项式寄存器块和差异寄存器块的相应输出的第一数据路径，执行与 校正和连接多项式的偶数系数，并输出偶数系数输出。 第二数据路径执行与校正连接多项式的奇数系数相关的预定操作，并输出奇数系数输出。 增量输出单元执行与连接多项式的偶数和奇数系数相关的预定操作并输出增量输出。 输出单元根据控制信号输出误差位置多项式的系数。 由于在操作过程中的延迟被最小化的Galois处理器具有小面积并且以高速操作，因此大大提高了解码器的性能。

    Method and apparatus for correcting C1/PI word errors using error locations detected by EFM/EFM+ decoding
    5.
    发明授权
    Method and apparatus for correcting C1/PI word errors using error locations detected by EFM/EFM+ decoding 失效
    使用由EFM / EFM +解码检测到的错误位置来校正C1 / PI字错误的方法和装置

    公开(公告)号：US07266748B2

    公开(公告)日：2007-09-04

    申请号：US10824407

    申请日：2004-04-14

    Applicant: Hyung-joon Kwon

    Inventor： Hyung-joon Kwon

    IPC: H03M13/29

    CPC classification number: G11B20/1866 ,  G11B20/1833

    Abstract: A method and system for error correcting C1/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including information data symbols and erasure flags by modulating channel data symbols, using the channel code; and (c) performing an error-erasure correction on the information data symbols of the demodulated data, using error locations indicated by the erasure flags. The system for channel decoding and error correcting includes a channel decoder with a channel code for producing the demodulated data having the information data symbols and the erasure flags by demodulating the channel data symbols, a memory for storing the demodulated data, and a decoding unit for performing an error-erasure correction on the information data symbols, using the error locations indicated by the erasure flags having a predetermined value.

    Abstract translation: 提供了一种使用由EFM / EFM +解码器检测到的错误位置对C 1 / PI字进行纠错的方法和系统。 信道解码和纠错方法包括：（a）建立信道码; （b）使用信道码，通过调制信道数据符号来产生包括信息数据符号和擦除标志的解调数据; 以及（c）使用由擦除标志指示的错误位置对解调数据的信息数据符号执行错误校正。 用于信道解码和纠错的系统包括具有信道码的信道解码器，用于产生具有信息数据符号的解调数据和通过解调信道数据符号的擦除标志，用于存储解调数据的存储器和用于 使用由具有预定值的擦除标志指示的错误位置对信息数据符号执行错误校正。

    Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device
    8.
    发明授权
    Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device 失效
    用于高速块流水线reed-solomon解码器的存储装置，存取装置的存取方法，以及具有存储装置的簧片独奏解码器

    公开(公告)号：US07586808B2

    公开(公告)日：2009-09-08

    申请号：US11396775

    申请日：2006-04-03

    Applicant: Hyung-joon Kwon ,  Il-man Bae

    Inventor： Hyung-joon Kwon ,  Il-man Bae

    IPC: G11C8/12

    CPC classification number: G06F11/1008 ,  G11C7/1039 ,  G11C8/12 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/1555 ,  H03M13/6566

    Abstract: A random access memory (RAM) device for use in a high-speed pipelined Reed-Solomon decoder, a method of accessing the memory device, and a Reed-Solomon decoder having the memory device are provided. The memory device, which data is written to and read from at the same time during decoding of one frame of data, includes a random access memory (RAM) having a plurality of banks; and a control circuit for setting a first bank pointer, which selects a first bank among the plurality of banks, and a second bank pointer which selects a second bank among the plurality of banks, wherein the first and second bank pointers are set to banks with a predetermined offset every frame of data.

    Abstract translation: 提供了用于高速流水线Reed-Solomon解码器的随机存取存储器（RAM）装置，访问存储器件的方法以及具有存储器件的Reed-Solomon解码器。 在一帧数据的解码期间，数据被写入和读取的存储器件包括具有多个存储体的随机存取存储器（RAM）; 以及控制电路，用于设置选择所述多个存储体中的第一存储体的第一存储体指针和选择所述多个存储体中的第二存储体的第二存储体指针，其中所述第一和第二存储体指针被设置为具有 每帧数据预定的偏移量。

    Minimum delay buffering method, minimum delay buffer device for dynamic write strategy, and CD-RW/DVD-RW system having the same
    9.
    发明授权
    Minimum delay buffering method, minimum delay buffer device for dynamic write strategy, and CD-RW/DVD-RW system having the same 失效
    最小延迟缓冲方法，动态写入策略的最小延迟缓冲器，以及具有相同功能的CD-RW / DVD-RW系统

    公开(公告)号：US07215615B2

    公开(公告)日：2007-05-08

    申请号：US10255335

    申请日：2002-09-26

    Applicant: Hyung-joon Kwon

    Inventor： Hyung-joon Kwon

    IPC: G11B7/0045

    CPC classification number: G11B20/10009 ,  G11B7/0045 ,  G11B7/006 ,  G11B2020/10759 ,  G11B2020/1461

    Abstract: A pattern buffer apparatus for a dynamic write strategy, which buffers non return to zero (NRZ) data patterns in order to generate a recording pulse in a compact disc system, includes a pattern detector which detects a pattern edge and a pattern from the NRZ data; a write address generating unit which generates a write address indicating a pattern buffer which stores the pattern in response to a write enable signal; the pattern buffer which has a plurality of registers and stores the detected pattern according to the write address; and a read address generating unit which generates a read address in response to a read enable signal, and reads the current pattern stored in the pattern buffer indicated by the read address.

    Abstract translation: 一种用于动态写入策略的图形缓冲装置，其缓冲不返回零（NRZ）数据模式以便在小型盘系统中产生记录脉冲，包括从NRZ数据检测模式边缘和模式的模式检测器 ; 写地址生成单元，其生成表示响应于写使能信号而存储所述模式的模式缓冲器的写入地址; 所述图案缓冲器具有多个寄存器并且根据所述写入地址存储所检测的图案; 以及读取地址生成单元，其响应于读取使能信号而生成读取地址，并读取由读取地址指示的模式缓冲器中存储的当前模式。

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