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    SEMICONDUCTOR MEMORY
    1.
    发明申请
    SEMICONDUCTOR MEMORY 有权
    半导体存储器

    公开(公告)号：US20100309708A1

    公开(公告)日：2010-12-09

    申请号：US12856850

    申请日：2010-08-16

    申请人： Kikuko SUGIMAE ,  Satoshi TANAKA ,  Koji HASHIMOTO ,  Masayuki ICHIGE

    发明人： Kikuko SUGIMAE ,  Satoshi TANAKA ,  Koji HASHIMOTO ,  Masayuki ICHIGE

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

    摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

    摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AAi，AAi + 1，...， 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

    NONVOLATILE SEMICONDUCTOR MEMORY, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR INTEGRATED CIRCUITS AND SYSTEMS
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR INTEGRATED CIRCUITS AND SYSTEMS 失效
    非线性半导体存储器，其制造方法，半导体集成电路和系统

    公开(公告)号：US20070070708A1

    公开(公告)日：2007-03-29

    申请号：US11559785

    申请日：2006-11-14

    申请人： Masayuki ICHIGE ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

    发明人： Masayuki ICHIGE ,  Koji Hashimoto ,  Tatsuaki Kuji ,  Seiichi Mori ,  Riichiro Shirota ,  Yuji Takeuchi ,  Koji Sakui

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524

    摘要： A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

    摘要翻译： 一种非易失性半导体存储器，被配置为包括沿行方向布置的多个字线; 沿垂直于字线的列方向布置的多个位线; 具有沿列方向设置的电荷存储层的存储单元晶体管和存储单元晶体管的电子存储状态，其被配置为由连接到存储单元的多条字线之一控制; 多个第一选择晶体管，每个包括栅极，选择沿列方向设置的存储单元晶体管，其布置在存储单元晶体管的第一端处并与存储单元晶体管相邻; 以及连接到第一选择晶体管的每个栅电极的第一选择栅极线。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20130015518A1

    公开(公告)日：2013-01-17

    申请号：US13353818

    申请日：2012-01-19

    申请人： Hiroyasu SATO ,  Kiyohito NISHIHARA ,  Hidefumi NAWATA ,  Masayuki ICHIGE ,  Ryuji OHBA

    发明人： Hiroyasu SATO ,  Kiyohito NISHIHARA ,  Hidefumi NAWATA ,  Masayuki ICHIGE ,  Ryuji OHBA

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7881 ,  H01L21/764 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825

    摘要： In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion.

    摘要翻译： 通常，根据一个实施例，半导体存储器件包括在第一方向上延伸的有源区域，设置在有源区域上的隧道膜，设置在隧道膜上的浮置栅极电极，设置在浮动栅电极上并延伸的电极间绝缘膜 在第二方向上，设置在电极间绝缘膜上并沿第二方向延伸的控制栅电极，设置在有源区之间，隧道膜之间以及在第二方向相邻的浮栅之间的下绝缘部分，以及 设置在下绝缘部和电极间绝缘膜之间的上绝缘部。 下绝缘部分包括空隙。 上绝缘部分的相对介电常数高于下绝缘部分的相对介电常数。 电极间绝缘膜的相对介电常数高于上绝缘部分。