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    Magnetic memory devices including oxide multiferroic material
    1.
    发明授权
    Magnetic memory devices including oxide multiferroic material 有权
    磁记忆装置包括氧化物多铁性材料

    公开(公告)号：US09424904B2

    公开(公告)日：2016-08-23

    申请号：US14526489

    申请日：2014-10-28

    申请人： Kilho Lee ,  Sangyong Kim ,  Woojin Kim ,  KyungTae Nam

    发明人： Kilho Lee ,  Sangyong Kim ,  Woojin Kim ,  KyungTae Nam

    IPC分类号： G11C11/02 ,  G11C11/16 ,  G11C11/22

    CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/221

    摘要： A magnetic memory device is provided. The magnetic memory device includes a plurality of variable resistance devices connected to a word line, and a plurality of bit lines, each of which provides an electrical pathway between a corresponding one of the variable resistance devices and a read and write circuit. Each of the variable resistance devices includes a free layer and a pinned layer spaced apart from each other and having a tunnel barrier interposed therebetween, an assistant layer spaced apart from the tunnel barrier and having the free layer interposed therebetween, and an exchange coupling layer arranged between the free layer and the assistant layer. The exchange coupling layer has an electric polarization, which results from its ferroelectric property, and having a direction that can be changed by a voltage applied to the corresponding one of the bit lines.

    摘要翻译： 提供磁存储器件。 磁存储器件包括连接到字线的多个可变电阻器件和多个位线，每个位线提供相应的一个可变电阻器件与读写电路之间的电路径。 每个可变电阻装置包括自由层和钉扎层，彼此间隔开并具有插入其间的隧道势垒，辅助层与隧道势垒间隔开并且具有插入其间的自由层，并且布置有交换耦合层 在自由层和辅助层之间。 交换耦合层具有由其铁电性质产生的电极化，并且具有可以通过施加到相应的一个位线的电压而改变的方向。

    Semiconductor memory devices
    2.
    发明授权
    Semiconductor memory devices 有权
    半导体存储器件

    公开(公告)号：US09595561B2

    公开(公告)日：2017-03-14

    申请号：US13951328

    申请日：2013-07-25

    申请人： Kilho Lee

    发明人： Kilho Lee

    IPC分类号： H01L27/22 ,  H01L29/78 ,  H01L27/115

    CPC分类号： H01L27/228 ,  H01L27/11585 ,  H01L29/78

    摘要： A semiconductor memory device includes a cell gate dielectric layer and a cell gate electrode disposed in a gate recess region crossing a cell active portion of a substrate, first and second doped regions disposed in the cell active portion at both sides of the gate recess region, respectively, at least one interlayer insulating layer covering the substrate, a data storage element electrically connected to the second doped region through a contact plug penetrating the at least one interlayer insulating layer, a mold layer covering the data storage element, and a bit line disposed in a cell groove formed in the mold layer. The bit line is in direct contact with a top surface of the data storage element.

    摘要翻译： 半导体存储器件包括：单元栅极电介质层和设置在与衬底的单元有源部分交叉的栅极凹部区域中的单元栅极电极，设置在栅极凹部区域两侧的单元有源部分中的第一和第二掺杂区域， 覆盖基板的至少一个层间绝缘层，通过穿透至少一个层间绝缘层的接触插塞电连接到第二掺杂区域的数据存储元件，覆盖数据存储元件的模具层和布置的位线 在模具层中形成的电池槽中。 位线与数据存储元件的顶表面直接接触。

    Semiconductor magnetic memory device and method for manufacturing the same
    3.
    发明授权
    Semiconductor magnetic memory device and method for manufacturing the same 有权
    半导体磁存储器件及其制造方法

    公开(公告)号：US09502291B2

    公开(公告)日：2016-11-22

    申请号：US14738814

    申请日：2015-06-12

    申请人： Kilho Lee ,  Shinhee Han

    发明人： Kilho Lee ,  Shinhee Han

    IPC分类号： H01L21/768 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    CPC分类号： H01L21/76877 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/4236 ,  H01L29/66621 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    摘要： A semiconductor memory device includes a first insulating layer covering a substrate, a first contact plug and a second contact plug each penetrating the first insulating layer, a first data storage element disposed on the first contact plug, and a second data storage element disposed on the second contact plug. The first contact plug includes a vertically extending portion and a horizontally extending portion arranged between the vertically extending portion and the first data storage element, and the second contact plug extends substantially vertically from a top surface of the substrate. The first data storage element is laterally spaced apart from the vertically extending portion when viewed in plan view. The first data storage element is disposed on the horizontally extending portion.

    摘要翻译： 半导体存储器件包括覆盖基片的第一绝缘层，每个穿透第一绝缘层的第一接触插塞和第二接触插塞，设置在第一接触插塞上的第一数据存储元件和设置在第一绝缘层上的第二数据存储元件 第二个接触插头 第一接触插塞包括垂直延伸部分和布置在垂直延伸部分和第一数据存储元件之间的水平延伸部分，并且第二接触插塞从衬底的顶表面基本垂直地延伸。 当在平面图中观察时，第一数据存储元件与垂直延伸部分横向间隔开。 第一数据存储元件设置在水平延伸部分上。

    MAGNETIC MEMORY DEVICES
    4.
    发明申请
    MAGNETIC MEMORY DEVICES 有权
    磁记忆装置

    公开(公告)号：US20160218145A1

    公开(公告)日：2016-07-28

    申请号：US14964251

    申请日：2015-12-09

    申请人： Shinhee Han ,  Kilho Lee ,  Yoonjong Song

    发明人： Shinhee Han ,  Kilho Lee ,  Yoonjong Song

    IPC分类号： H01L27/22 ,  G11C11/16 ,  H01L43/02

    CPC分类号： H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L27/226 ,  H01L43/08 ,  H01L43/12

    摘要： Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

    摘要翻译： 提供磁存储器件。 磁存储器件包括在触点上的磁隧道结（MTJ）结构。 此外，磁存储器件包括绝缘结构和MTJ结构与触点之间的电极。 在一些实施例中，具有MTJ结构的电极的第一接触面积小于具有MTJ结构的绝缘结构的第二接触面积。

    Dual gate oxide process without critical resist and without N2 implant
    5.
    发明授权
    Dual gate oxide process without critical resist and without N2 implant 有权
    双栅氧化物工艺，无需临界抗蚀剂，无N2注入

    公开(公告)号：US06579766B1

    公开(公告)日：2003-06-17

    申请号：US10077518

    申请日：2002-02-15

    申请人： Helmut H. Tews ,  Ravikumar Ramachandran ,  Kilho Lee

    发明人： Helmut H. Tews ,  Ravikumar Ramachandran ,  Kilho Lee

    IPC分类号： H01L21336

    CPC分类号： H01L21/823857

    摘要： A process as shown in FIGS. 1A through 1I, or FIGS. 2A through 2I for providing first areas of gate oxide (30, 30A, 30B) on a substrate (10) having a first thickness and second adjacent areas (32, 32A, 32B) of gate oxide having a lesser thickness without the use of a N2 implantation process.

    摘要翻译： 如图1和图2所示的处理。 图1A至图1I， 用于在具有第一厚度的衬底（10）上提供栅极氧化物（30,30A，30B）的第一区域，以及具有较小厚度的栅极氧化物的第二相邻区域（32,32A，32B），而不使用 N2植入工艺。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10164170B2

    公开(公告)日：2018-12-25

    申请号：US15622064

    申请日：2017-06-13

    申请人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

    发明人： Kiseok Suh ,  Byoungjae Bae ,  Gwanhyeob Koh ,  Yoonjong Song ,  Kilho Lee

    IPC分类号： H01L43/02 ,  H01L43/08 ,  H01L27/22

    摘要： A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.

    Memory devices
    7.
    发明授权
    Memory devices 有权
    内存设备

    公开(公告)号：US08872270B2

    公开(公告)日：2014-10-28

    申请号：US13686212

    申请日：2012-11-27

    申请人： Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

    发明人： Kilho Lee ,  Ki Joon Kim ,  Se-Woong Park

    IPC分类号： H01L21/70 ,  H01L29/82 ,  H01L27/108

    CPC分类号： H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

    摘要： Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

    摘要翻译： 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。