公开(公告)号：US20220328103A1

公开(公告)日：2022-10-13

申请号：US17852683

申请日：2022-06-29

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Kenta YASUFUKU ,  Akira YAMAGA

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

公开(公告)号：US20220092002A1

公开(公告)日：2022-03-24

申请号：US17198676

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Kenta YASUFUKU

IPC: G06F13/16 ,  G06F12/0891 ,  G06F12/0871

Abstract: According to an embodiment, a memory system includes a controller which includes an interface connectable with a host with cache coherency kept. The controller is configured to: before the host writes a command to an I/O submission queue, read the I/O submission queue; after the reading, detect via the interface an invalidation request, the invalidation request being based on writing of the command by the host to the I/O submission queue; and in response to the invalidation request, acquire the command in the I/O submission queue.

公开(公告)号：US20230420052A1

公开(公告)日：2023-12-28

申请号：US18466344

申请日：2023-09-13

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Kenta YASUFUKU ,  Akira YAMAGA

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/34 ,  G11C16/26 ,  G11C2211/5641 ,  G11C11/5642

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

公开(公告)号：US20220308766A1

公开(公告)日：2022-09-29

申请号：US17458135

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Shohei ONISHI ,  Kenta YASUFUKU

IPC: G06F3/06

Abstract: A memory controller connectable to a semiconductor memory including a plurality of memory areas, includes a counter circuit configured to count a degree of wear of each of the memory areas in response to a memory operation addressed thereto, and a control circuit configured to set a rate of for wear leveling to be performed on the plurality of memory areas based on a total number of memory operations performed thereon, and select whether to perform wear leveling on each of the memory areas based on the rate, the degree of wear counted for the memory area, a first threshold for the degree of wear, and a second threshold for the degree of wear. The second threshold is greater than the first threshold.

公开(公告)号：US20250037771A1

公开(公告)日：2025-01-30

申请号：US18918966

申请日：2024-10-17

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Kenta YASUFUKU ,  Akira YAMAGA

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

公开(公告)号：US20240078174A1

公开(公告)日：2024-03-07

申请号：US18461217

申请日：2023-09-05

Applicant: Kioxia Corporation

Inventor： Takeshi ISHIHARA ,  Yohei HASEGAWA ,  Kenta YASUFUKU ,  Shohei ONISHI ,  Yoshiki SAITO ,  Junpei KIDA

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: An information storage device includes a storage unit, a control unit, an allocation information storage unit, a QoS parameter storage unit, and a monitoring result storage unit. The control unit creates and manages a logical storage area using the storage area of the storage unit when a storage area allocation request is received. The allocation information storage unit stores allocation information related to logical storage areas. The QoS parameter storage unit stores quality requests expected to be satisfied for a communication for using the logical storage area. The control unit monitors the operating state and characteristics of the storage unit and the communication status, and stores the results in the monitoring result storage unit. The control unit derives internal QoS parameters to be set in the information storage device from the information stored in the allocation information storage unit, the QoS parameter storage unit, and the monitoring result storage unit.

公开(公告)号：US20230409229A1

公开(公告)日：2023-12-21

申请号：US18178422

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Akifumi FUKUDA ,  Kenta YASUFUKU

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0604

Abstract: A memory system includes a non-volatile memory and a controller including a memory having a lower access latency than the non-volatile memory. The controller is configured to track addresses of data stored in the non-volatile memory that were subject to prior wear leveling processes, in a buffer configured in the memory of the controller, perform a current wear leveling process on data stored in the non-volatile memory, and determine whether an address of the data subject to the current wear leveling process is stored in the buffer, and perform a pinning process to disable overwrite of data stored in the memory of the controller and corresponding to the address.