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公开(公告)号：US4949213A
公开(公告)日：1990-08-14
申请号：US436643
申请日：1989-11-15
IPC分类号： H03K17/0812 , H03K17/082 , H03K17/567 , H03K17/615
CPC分类号： H03K17/0828 , H03K17/08128 , H03K17/567 , H03K17/615
摘要： In a common drive output circuit for driving dissimilar switching semiconductor devices having different drive input characteristics by turning on and off dc power supplies to apply a voltage between the drive input terminals of either one of the switching semiconductor devices through two transistors connected in a Darlington pair, the collector circuit of one of the two transistors which is not at the output stage has a diode inserted in series which has such a polarity as to permit passage of the collector current.
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公开(公告)号：US5200878A
公开(公告)日：1993-04-06
申请号：US729436
申请日：1991-07-12
申请人： Kiyoaki Sasagawa , Hiroshi Miki
发明人： Kiyoaki Sasagawa , Hiroshi Miki
IPC分类号： H02M3/145 , H02M1/00 , H03K17/082
CPC分类号： H03K17/0828
摘要： A drive circuit for a current sense IGBT having, in addition to a fault discrimination operational circuit for detecting an overcurrent of the current sense IGBT, a capacitor operatively connected in parallel to the gate-emitter of the current sense IGBT, and a transistor for discharging the capacitor via a resistor. In case of short-circuit fault, an overcurrent is detected by the fault discrimination operational circuit, and the transistor is turned on via the operational circuit. The gate voltage of the IGBT is gradually declined to turn off the IGBT. This enables the IGBT to be protected from a transitional overvoltage across the collector and emitter of the IGBT.
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公开(公告)号：US5200879A
公开(公告)日：1993-04-06
申请号：US729480
申请日：1991-07-12
申请人： Kiyoaki Sasagawa , Hiroshi Miki
发明人： Kiyoaki Sasagawa , Hiroshi Miki
IPC分类号： H02M3/155 , H02M1/00 , H02M1/08 , H03K17/00 , H03K17/082 , H03K17/785
CPC分类号： H03K17/785 , H03K17/0822 , H03K17/0828 , H03K2217/0036
摘要： A drive circuit for a voltage driven type semiconductor device having a serial circuit of a resistor and a Zener diode. One terminal of the serial circuit is connected to an output terminal (collector) of the semiconductor device. An overcurrent flowing in the semiconductor device is detected based on a current flowing through the serial circuit and the presence or absence of a drive signal fed to the drive circuit from an external control circuit. The detection level of the overcurrent can be adjusted by the voltage of the Zener diode, and the quick detection becomes possible. This arrangement makes it possible to detect an overcurrent in the semiconductor device, and hence to detect a shortcircuit in a circuit connected to that device in a minimal time required, thereby reducing the energy consumed in the semiconductor device during the short circuit.
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公开(公告)号：US20120097533A1
公开(公告)日：2012-04-26
申请号：US13316927
申请日：2011-12-12
申请人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
发明人： Shuji NOMURA , Ayumu Miyoshi , Hiroshi Miki
IPC分类号： C23C14/34
CPC分类号： C23C14/3464
摘要： A sputtering apparatus including a target holder configured to hold at least two targets; a substrate holder configured to hold a substrate; a first shutter plate arranged between the target holder and the substrate holder, the first shutter plate having at least two holes and being capable of rotating around an axis; a second shutter plate arranged between the first shutter plate and the substrate holder, the second shutter plate having at least two holes and being capable of rotating around the axis; wherein the first and second shutter plates are rotated such that paths are simultaneously created between the at least two targets and the substrate through the at least two holes of the rotated first shutter plate and the at least two holes of the rotated second shutter plate, and a film is formed on the substrate by co-sputtering of the at least two targets.
摘要翻译： 一种溅射装置，包括被配置为保持至少两个靶的目标支架; 衬底保持器，其构造成保持衬底; 布置在所述目标保持器和所述基板保持器之间的第一挡板，所述第一挡板具有至少两个孔并且能够绕轴线旋转; 布置在所述第一活门板和所述衬底支架之间的第二活门板，所述第二活门板具有至少两个孔并能绕所述轴线旋转; 其中所述第一和第二快门板旋转，使得通过旋转的第一快门板的至少两个孔和旋转的第二快门板的至少两个孔同时在至少两个目标和基板之间产生通路，以及 通过共溅射至少两个靶，在衬底上形成膜。
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公开(公告)号：US20070228427A1
公开(公告)日：2007-10-04
申请号：US11723683
申请日：2007-03-21
申请人： Yuichi Matsui , Hiroshi Miki
发明人： Yuichi Matsui , Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L27/10852 , H01L21/02175 , H01L21/022 , H01L21/02271 , H01L21/31641 , H01L21/31645 , H01L27/10814 , H01L27/10894 , H01L28/91
摘要： HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.
摘要翻译： 目前正在开发用于85nm技术节点DRAM中的电容器电介质膜的HfO 2膜和ZrO 2膜。 然而，这些膜将难以在65nm技术节点或之后的DRAM中使用，因为它们的相对介电常数只有20-25。 这些膜的介电常数可以通过稳定它们的立方相来增加。 然而，这导致沿着晶粒边界的漏电流的增加，这使得难以将这些膜用作电容器电介质膜。 为了克服这个问题，本发明将HfO 2 2或ZrO 2 2的基材与具有大离子半径的元素的氧化物如Y或La掺杂， 以增加基材的氧配位数，从而即使当基材处于非晶状态时，其相对介电常数也提高到30以上。 因此，本发明提供可用于形成满足65nm技术节点或更高版本的DRAM电容器的电介质膜。
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公开(公告)号：US07034355B2
公开(公告)日：2006-04-25
申请号：US10496000
申请日：2002-12-02
申请人： Hiroshi Miki
发明人： Hiroshi Miki
IPC分类号： H01L29/76
CPC分类号： H01L21/28211 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/511
摘要： To achieve a higher operating speed, higher reliability, and lower power consumption by reducing the thickness of an inter-poly silicon insulator film between a floating gate and a control gate of a flash memory, a silicon dioxide film, a silicon nitride film, tantalum pentoxide, and a silicon dioxide film are formed in a multilayer structure to serve as the inter-poly insulator film between a floating gate and a control gate. With this configuration, tantalum pentoxide formed on the silicon nitride film has a dielectric constant of 50 or more, which is higher than that of the silicon dioxide film, and the thickness of the inter-poly silicon insulator film can be reduced.
摘要翻译： 为了通过减小浮动栅极和闪速存储器的控制栅极之间的多晶硅绝缘膜的厚度来实现更高的操作速度，更高的可靠性和更低的功率消耗，二氧化硅膜，氮化硅膜，钽 五氧化物和二氧化硅膜形成为多层结构，以用作浮置栅极和控制栅极之间的多晶硅绝缘膜。 利用这种构造，形成在氮化硅膜上的五氧化二钽的介电常数为50以上，高于二氧化硅膜的介电常数，能够降低多晶硅绝缘膜的厚度。
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公开(公告)号：US06822276B1
公开(公告)日：2004-11-23
申请号：US09391250
申请日：1999-09-07
IPC分类号： H01L27108
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： It is an object of the present invention to provide a fine memory cell structure preventing a reaction between an interlayer insulating film and a ferroelectric film and suitable for high integration. According to the invention, there is provided a structure in which a reaction barrier film 43 is interposed between a ferroelectric film 71 and an interlayer insulating film 32 and side walls of a diffusion barrier film 51 are not brought into direct contact with the ferroelectric film 71. Thereby, the reaction between the interlayer insulating film 32 and the ferroelectric film 71 can be restrained and exfoliation of the ferroelectric film 71 can be prevented.
摘要翻译： 本发明的目的是提供一种防止层间绝缘膜和铁电体膜之间的反应并且适合于高集成度的精细存储单元结构。 根据本发明，提供一种结构，其中反应阻挡膜43介于铁电膜71和层间绝缘膜32之间，并且扩散阻挡膜51的侧壁不与铁电体膜71直接接触 由此，能够抑制层间绝缘膜32与强电介质膜71的反应，能够防止铁电体膜71的剥离。
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公开(公告)号：US06800889B2
公开(公告)日：2004-10-05
申请号：US10073240
申请日：2002-02-13
IPC分类号： H01L2976
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。
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公开(公告)号：US06509246B2
公开(公告)日：2003-01-21
申请号：US09877207
申请日：2001-06-11
IPC分类号： H01L2120
CPC分类号： H01L28/84 , H01L27/10814 , H01L28/91
摘要： A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.
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公开(公告)号：US06462368B2
公开(公告)日：2002-10-08
申请号：US10059256
申请日：2002-01-31
IPC分类号： H01L2976
CPC分类号： H01L27/10855 , H01L21/76885 , H01L27/10894 , H01L28/91
摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的扩散层之一的互连之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以制造侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞也不与电介质膜直接接触 具有很高的介电常数。 因此，可以获得高度可靠的装置。
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