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1.发明授权Transfer control technique between two units included in a data processing system 失效包括在数据处理系统中的两个单元之间的传输控制技术
公开(公告)号：US4225921A
公开(公告)日：1980-09-30
申请号：US947990
申请日：1978-10-02
CPC分类号： G06F9/226 , G06F13/4239
摘要： A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.
摘要翻译： 数据处理单元响应于来自该单元的指令传送控制和处理操作的数据处理设备的请求被设备停止，取决于指令的类型一段时间，也依赖于 对指令的类型，直到设备准备好处理这样的操作。 在设备中使用移位寄存器装置，其根据存储在其中的标记，根据指令的类型将哪个标记适当地加载在这样的寄存器中，用于通过请求单元进行另一个来延迟对单元的响应 请求设备处理由指令调用的操作。
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2.发明授权
公开(公告)号：US4236210A
公开(公告)日：1980-11-25
申请号：US947987
申请日：1978-10-02
CPC分类号： G06F9/268 , G06F9/30189 , G06F9/30196 , G06F9/328 , G06F9/3869
摘要： A control store coupled with a central processing unit to transfer information over a common electrical bus and coupled to transfer information over a private interface between the control store and unit. The control store includes firmware words for providing additional control of the unit, which also has a control memory for controlling the operation of the unit. The private interface is used to transfer addressed firmware words from the control store to the unit for use by the unit including generating the next address to be used by the control store, which next address is also provided from the unit to the control store over the private interface. Such private interface is also used to transfer the results of one or more tests performed by the unit, which results indicate which of at least two alternative addresses are to be used by the control store.
摘要翻译： 控制存储器与中央处理单元耦合，以通过公共电总线传送信息，并耦合以通过控制存储器和单元之间的专用接口传送信息。 控制存储器包括用于提供对该单元的附加控制的固件字，该单元还具有用于控制单元操作的控制存储器。 私有接口用于将寻址的固件字从控制存储器传送到单元以供该单元使用，包括生成由控制存储器使用的下一个地址，下一个地址也从该单元通过该单元提供给控制存储器 私有接口。 这种专用接口还用于传送由该单元执行的一个或多个测试的结果，其结果指示控制存储器将使用至少两个备选地址中的哪一个。
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3.发明授权State machine for executing commands within a minimum number of cycles by accomodating unforseen time dependency according to status signals received from different functional sections 失效用于通过根据从不同功能部分接收的状态信号来容纳不可见的时间依赖来在最小数量的周期内执行命令的状态机
公开(公告)号：US5280595A
公开(公告)日：1994-01-18
申请号：US593923
申请日：1990-10-05
摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.
摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。
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公开(公告)号：US4811266A
公开(公告)日：1989-03-07
申请号：US927630
申请日：1986-11-05
申请人： William E. Woods , Richard A. Lemay
发明人： William E. Woods , Richard A. Lemay
CPC分类号： G06F7/57 , G06F2207/382 , G06F7/49905 , G06F7/4991
摘要： A multifunction arithmetic indicator that is associated with and controlled by an arithmetic logic unit (ALU) to store standard arithmetic indicator information such as overflow, carry, arithmetic sign and all bits equal zero that are generated by the ALU when processing binary information. A control unit sends control signals to multiplexers in the multifunction arithmetic indicator that cause the selection of appropriate arithmetic indicator information from the ALU, no matter what the bit length of binary words being processed by the ALU. The selected indicator information is stored in a register for later use.
摘要翻译： 一种与运算逻辑单元（ALU）相关联和控制的多功能运算指示器，用于存储当处理二进制信息时由ALU产生的诸如溢出，进位，算术符号和全部位相等的零的标准运算指示符信息。 控制单元向多功能运算指示器中的多路复用器发送控制信号，导致从ALU选择合适的算术指示符信息，无论ALU处理二进制字的位长是多少。 选择的指示符信息存储在寄存器中供以后使用。
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公开(公告)号：US4467417A
公开(公告)日：1984-08-21
申请号：US302903
申请日：1981-09-16
CPC分类号： G06F9/30181 , G06F9/3016 , G06F9/325
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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6.发明授权
公开(公告)号：US4349874A
公开(公告)日：1982-09-14
申请号：US140630
申请日：1980-04-15
CPC分类号： G06F12/0862 , G06F2212/6022
摘要： In a data processing system, a central processor unit requests procedural data words or non-procedural data words stored in the system memory. A control store device executes firmware instructions including a local bus field for controlling the transfer of the requested procedural data words and non-procedural data words to the central processor unit. The requested procedural data words and non-procedural data words are transferred to the central processing unit by an interfacing device including a data bus latch for receiving the procedural data words and non-procedural data words transferred from the memory, a prefetch buffer for storing up to four words, a first set of OR gate circuits for selectively transferring the procedural data words stored in the prefetch buffer to a procedural data multiplexer for assembling either a procedural data word or a procedure address, and a second set of OR gate circuits for selectively transferring either a procedural data word or non-procedural data word to the source bus or a procedural data address or non-procedural data address to the source bus for transfer to the central processor unit.
摘要翻译： 在数据处理系统中，中央处理器单元请求存储在系统存储器中的过程数据字或非程序数据字。 控制存储设备执行固件指令，其包括本地总线字段，用于控制所请求的过程数据字和非程序数据字向中央处理器单元的传送。 所请求的程序数据字和非程序数据字通过包括用于接收程序数据字的数据总线锁存器和从存储器传送的非程序数据字的接口装置传送到中央处理器，用于存储的预取缓冲器 四个字，第一组OR门电路，用于选择性地将存储在预取缓冲器中的程序数据字传送到程序数据多路复用器，用于组装程序数据字或程序地址，以及第二组OR门电路，用于选择性地 将程序数据字或非程序数据字传送到源总线或程序数据地址或非程序数据地址到源总线以传送到中央处理器单元。
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公开(公告)号：US4245299A
公开(公告)日：1981-01-13
申请号：US867262
申请日：1978-01-05
CPC分类号： G06F13/378 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data.
摘要翻译： 在包括诸如数据处理系统之类的多个单元连接的公共总线的系统中，在异步生成的总线传送周期期间，信息可以由最高优先级单元传送。 逻辑被提供用于使第一单元（例如中央处理器）能够在第一传送周期期间进行诸如存储器的第二单元的多次提取请求。 多次提取请求请求第二单元在多个其它传送周期期间将多个数据部分传送到第一单元，其中在每个进一步的传送周期中传送一部分数据。 在第二单元中提供逻辑以使第二单元能够向第一单元指示，除了在最后一个进一步的传送周期内，每个进一步的传送周期将跟随另一传送周期。 在第一单元中提供逻辑以使得第一单元能够接收比原来在多次提取请求中要求的更少的数据部分。 这允许第一单元在总线上进行其他单元的多个提取请求，而不考虑其他单元是否能够执行多次获取操作，并且不需要第二单元中的异常状态恢复逻辑。 还提供逻辑以允许第一单元利用第一单元接收的数据的每个部分，而不需要第一单元在使用任何接收的数据部分之前等待最后的传送周期。
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公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
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9.发明授权Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories 失效通过选择性地将状态信号分组为输入并将待执行的命令分类为性能敏感和非敏感类别来组织状态机的方法
公开(公告)号：US5375248A
公开(公告)日：1994-12-20
申请号：US99117
申请日：1993-07-29
摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.
摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。
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10.发明授权Buffered address stack register with parallel input registers and overflow protection 失效缓冲地址堆栈寄存器具有并行输入寄存器和溢出保护
公开(公告)号：US5161217A
公开(公告)日：1992-11-03
申请号：US418084
申请日：1989-10-06
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.
摘要翻译： 一个具有多个地址输入端口并且能够存储多个地址的先进先出寄存器。 地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。 当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后存储在寄存器中的附加地址，以及随后传送到存储器的地址 用于存储重新发送到缓冲地址寄存器以进行读出。
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